180 lines
3.1 KiB
Plaintext
180 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
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*
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* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Horatiu Vultur <horatiu.vultur@microchip.com>
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*/
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/dts-v1/;
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#include "lan966x.dtsi"
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#include "dt-bindings/phy/phy-lan966x-serdes.h"
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/ {
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model = "Microchip EVB LAN9668";
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compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
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priority = <200>;
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};
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};
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&aes {
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status = "disabled"; /* Reserved by secure OS */
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};
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&gpio {
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miim_a_pins: mdio-pins {
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/* MDC, MDIO */
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pins = "GPIO_28", "GPIO_29";
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function = "miim_a";
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};
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pps_out_pins: pps-out-pins {
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/* 1pps output */
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pins = "GPIO_38";
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function = "ptpsync_3";
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};
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ptp_ext_pins: ptp-ext-pins {
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/* 1pps input */
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pins = "GPIO_35";
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function = "ptpsync_0";
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};
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udc_pins: ucd-pins {
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/* VBUS_DET B */
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pins = "GPIO_8";
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function = "usb_slave_b";
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};
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};
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&mdio0 {
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pinctrl-0 = <&miim_a_pins>;
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pinctrl-names = "default";
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status = "okay";
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ext_phy0: ethernet-phy@7 {
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reg = <7>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy1: ethernet-phy@8 {
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reg = <8>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy2: ethernet-phy@9 {
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reg = <9>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy3: ethernet-phy@10 {
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reg = <10>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy4: ethernet-phy@15 {
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reg = <15>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy5: ethernet-phy@16 {
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reg = <16>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy6: ethernet-phy@17 {
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reg = <17>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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ext_phy7: ethernet-phy@18 {
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reg = <18>;
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coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
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};
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};
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&port0 {
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reg = <2>;
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phy-handle = <&ext_phy2>;
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phy-mode = "qsgmii";
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phys = <&serdes 0 SERDES6G(1)>;
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status = "okay";
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};
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&port1 {
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reg = <3>;
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phy-handle = <&ext_phy3>;
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phy-mode = "qsgmii";
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phys = <&serdes 1 SERDES6G(1)>;
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status = "okay";
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};
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&port2 {
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reg = <0>;
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phy-handle = <&ext_phy0>;
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phy-mode = "qsgmii";
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phys = <&serdes 2 SERDES6G(1)>;
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status = "okay";
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};
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&port3 {
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reg = <1>;
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phy-handle = <&ext_phy1>;
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phy-mode = "qsgmii";
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phys = <&serdes 3 SERDES6G(1)>;
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status = "okay";
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};
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&port4 {
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reg = <6>;
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phy-handle = <&ext_phy6>;
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phy-mode = "qsgmii";
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phys = <&serdes 4 SERDES6G(2)>;
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status = "okay";
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};
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&port5 {
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reg = <7>;
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phy-handle = <&ext_phy7>;
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phy-mode = "qsgmii";
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phys = <&serdes 5 SERDES6G(2)>;
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status = "okay";
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};
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&port6 {
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reg = <4>;
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phy-handle = <&ext_phy4>;
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phy-mode = "qsgmii";
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phys = <&serdes 6 SERDES6G(2)>;
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status = "okay";
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};
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&port7 {
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reg = <5>;
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phy-handle = <&ext_phy5>;
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phy-mode = "qsgmii";
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phys = <&serdes 7 SERDES6G(2)>;
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status = "okay";
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};
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&serdes {
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status = "okay";
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};
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&switch {
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pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&udc {
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pinctrl-0 = <&udc_pins>;
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pinctrl-names = "default";
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atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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