555 lines
15 KiB
Plaintext
555 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung Exynos5260 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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#include <dt-bindings/clock/exynos5260-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "samsung,exynos5260", "samsung,exynos5";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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i2c0 = &hsi2c_0;
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i2c1 = &hsi2c_1;
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i2c2 = &hsi2c_2;
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i2c3 = &hsi2c_3;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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core2 {
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cpu = <&cpu4>;
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};
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core3 {
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cpu = <&cpu5>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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cci-control-port = <&cci_control0>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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cci-control-port = <&cci_control0>;
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};
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cpu4: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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cci-control-port = <&cci_control0>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock_top: clock-controller@10010000 {
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compatible = "samsung,exynos5260-clock-top";
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reg = <0x10010000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_mif MIF_DOUT_MEM_PLL>,
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<&clock_mif MIF_DOUT_BUS_PLL>,
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<&clock_mif MIF_DOUT_MEDIA_PLL>;
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clock-names = "fin_pll",
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"dout_mem_pll",
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"dout_bus_pll",
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"dout_media_pll";
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};
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clock_peri: clock-controller@10200000 {
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compatible = "samsung,exynos5260-clock-peri";
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reg = <0x10200000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&ioclk_pcm>,
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<&ioclk_i2s>,
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<&ioclk_spdif>,
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<&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_PERI_66>,
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<&clock_top TOP_DOUT_SCLK_PERI_UART0>,
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<&clock_top TOP_DOUT_SCLK_PERI_UART1>,
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<&clock_top TOP_DOUT_SCLK_PERI_UART2>,
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<&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
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<&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
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<&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
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<&clock_top TOP_DOUT_ACLK_PERI_AUD>;
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clock-names = "fin_pll",
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"ioclk_pcm_extclk",
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"ioclk_i2s_cdclk",
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"ioclk_spdif_extclk",
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"phyclk_hdmi_phy_ref_cko",
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"dout_aclk_peri_66",
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"dout_sclk_peri_uart0",
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"dout_sclk_peri_uart1",
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"dout_sclk_peri_uart2",
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"dout_sclk_peri_spi0_b",
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"dout_sclk_peri_spi1_b",
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"dout_sclk_peri_spi2_b",
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"dout_aclk_peri_aud";
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};
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clock_egl: clock-controller@10600000 {
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compatible = "samsung,exynos5260-clock-egl";
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reg = <0x10600000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_mif MIF_DOUT_BUS_PLL>;
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clock-names = "fin_pll",
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"dout_bus_pll";
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};
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clock_kfc: clock-controller@10700000 {
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compatible = "samsung,exynos5260-clock-kfc";
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reg = <0x10700000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_mif MIF_DOUT_MEDIA_PLL>;
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clock-names = "fin_pll",
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"dout_media_pll";
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};
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clock_g2d: clock-controller@10a00000 {
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compatible = "samsung,exynos5260-clock-g2d";
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reg = <0x10A00000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_G2D_333>;
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clock-names = "fin_pll",
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"dout_aclk_g2d_333";
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};
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clock_mif: clock-controller@10ce0000 {
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compatible = "samsung,exynos5260-clock-mif";
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reg = <0x10CE0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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clock_mfc: clock-controller@11090000 {
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compatible = "samsung,exynos5260-clock-mfc";
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reg = <0x11090000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_MFC_333>;
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clock-names = "fin_pll",
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"dout_aclk_mfc_333";
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};
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clock_g3d: clock-controller@11830000 {
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compatible = "samsung,exynos5260-clock-g3d";
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reg = <0x11830000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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clock_fsys: clock-controller@122e0000 {
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compatible = "samsung,exynos5260-clock-fsys";
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reg = <0x122E0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_FSYS_200>;
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clock-names = "fin_pll",
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"phyclk_usbhost20_phy_phyclock",
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"phyclk_usbhost20_phy_freeclk",
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"phyclk_usbhost20_phy_clk48mohci",
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"phyclk_usbdrd30_udrd30_pipe_pclk",
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"phyclk_usbdrd30_udrd30_phyclock",
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"dout_aclk_fsys_200";
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};
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clock_aud: clock-controller@128c0000 {
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compatible = "samsung,exynos5260-clock-aud";
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reg = <0x128C0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_top TOP_FOUT_AUD_PLL>,
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<&ioclk_i2s>,
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<&ioclk_pcm>;
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clock-names = "fin_pll",
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"fout_aud_pll",
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"ioclk_i2s_cdclk",
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"ioclk_pcm_extclk";
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};
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clock_isp: clock-controller@133c0000 {
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compatible = "samsung,exynos5260-clock-isp";
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reg = <0x133C0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_ISP1_266>,
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<&clock_top TOP_DOUT_ACLK_ISP1_400>,
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<&clock_top TOP_MOUT_ACLK_ISP1_266>;
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clock-names = "fin_pll",
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"dout_aclk_isp1_266",
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"dout_aclk_isp1_400",
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"mout_aclk_isp1_266";
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};
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clock_gscl: clock-controller@13f00000 {
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compatible = "samsung,exynos5260-clock-gscl";
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reg = <0x13F00000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_top TOP_DOUT_ACLK_GSCL_400>,
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<&clock_top TOP_DOUT_ACLK_GSCL_333>;
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clock-names = "fin_pll",
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"dout_aclk_gscl_400",
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"dout_aclk_gscl_333";
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};
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clock_disp: clock-controller@14550000 {
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compatible = "samsung,exynos5260-clock-disp";
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reg = <0x14550000 0x10000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&fin_pll>,
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<&ioclk_spdif>,
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<&clock_top TOP_DOUT_ACLK_PERI_AUD>,
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<&clock_top TOP_DOUT_ACLK_DISP_222>,
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<&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
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<&clock_top TOP_DOUT_ACLK_DISP_333>;
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clock-names = "fin_pll",
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"phyclk_dptx_phy_ch3_txd_clk",
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"phyclk_dptx_phy_ch2_txd_clk",
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"phyclk_dptx_phy_ch1_txd_clk",
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"phyclk_dptx_phy_ch0_txd_clk",
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"phyclk_hdmi_phy_tmds_clko",
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"phyclk_hdmi_phy_ref_clko",
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"phyclk_hdmi_phy_pixel_clko",
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"phyclk_hdmi_link_o_tmds_clkhi",
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"phyclk_mipi_dphy_4l_m_txbyte_clkhs",
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"phyclk_dptx_phy_o_ref_clk_24m",
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"phyclk_dptx_phy_clk_div2",
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"phyclk_mipi_dphy_4l_m_rxclkesc0",
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"phyclk_hdmi_phy_ref_cko",
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"ioclk_spdif_extclk",
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"dout_aclk_peri_aud",
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"dout_aclk_disp_222",
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"dout_sclk_disp_pixel",
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"dout_aclk_disp_333";
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};
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gic: interrupt-controller@10481000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10481000 0x1000>,
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<0x10482000 0x2000>,
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<0x10484000 0x2000>,
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<0x10486000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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chipid: chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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mct: timer@100b0000 {
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compatible = "samsung,exynos5260-mct",
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"samsung,exynos4210-mct";
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reg = <0x100B0000 0x1000>;
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clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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};
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cci: cci@10f00000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10F00000 0x1000>;
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ranges = <0x0 0x10F00000 0x6000>;
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cci_control0: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control1: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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pinctrl_0: pinctrl@11600000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x11600000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_1: pinctrl@12290000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x12290000 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_2: pinctrl@128b0000 {
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compatible = "samsung,exynos5260-pinctrl";
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reg = <0x128B0000 0x1000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu_system_controller: system-controller@10d50000 {
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compatible = "samsung,exynos5260-pmu", "syscon";
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reg = <0x10D50000 0x10000>;
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};
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uart0: serial@12c00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart1: serial@12c10000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C10000 0x100>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart2: serial@12c20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C20000 0x100>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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uart3: serial@12860000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12860000 0x100>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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mmc_0: mmc@12140000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12140000 0x2000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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assigned-clocks =
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<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
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<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
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<&clock_top TOP_SCLK_MMC0>;
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assigned-clock-parents =
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<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
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<&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
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assigned-clock-rates = <0>, <0>, <800000000>;
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fifo-depth = <64>;
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status = "disabled";
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};
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mmc_1: mmc@12150000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12150000 0x2000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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assigned-clocks =
|
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<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
|
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<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
|
|
<&clock_top TOP_SCLK_MMC1>;
|
|
assigned-clock-parents =
|
|
<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
|
|
<&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
|
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assigned-clock-rates = <0>, <0>, <800000000>;
|
|
fifo-depth = <64>;
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|
status = "disabled";
|
|
};
|
|
|
|
mmc_2: mmc@12160000 {
|
|
compatible = "samsung,exynos5250-dw-mshc";
|
|
reg = <0x12160000 0x2000>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
|
|
clock-names = "biu", "ciu";
|
|
assigned-clocks =
|
|
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
|
|
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
|
|
<&clock_top TOP_SCLK_MMC2>;
|
|
assigned-clock-parents =
|
|
<&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
|
|
<&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
|
|
assigned-clock-rates = <0>, <0>, <800000000>;
|
|
fifo-depth = <64>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_0: i2c@12da0000 {
|
|
compatible = "samsung,exynos5260-hsi2c";
|
|
reg = <0x12DA0000 0x1000>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_hs_bus>;
|
|
clocks = <&clock_peri PERI_CLK_HSIC0>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_1: i2c@12db0000 {
|
|
compatible = "samsung,exynos5260-hsi2c";
|
|
reg = <0x12DB0000 0x1000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_hs_bus>;
|
|
clocks = <&clock_peri PERI_CLK_HSIC1>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_2: i2c@12dc0000 {
|
|
compatible = "samsung,exynos5260-hsi2c";
|
|
reg = <0x12DC0000 0x1000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_hs_bus>;
|
|
clocks = <&clock_peri PERI_CLK_HSIC2>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_3: i2c@12dd0000 {
|
|
compatible = "samsung,exynos5260-hsi2c";
|
|
reg = <0x12DD0000 0x1000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_hs_bus>;
|
|
clocks = <&clock_peri PERI_CLK_HSIC3>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "exynos5260-pinctrl.dtsi"
|