644 lines
15 KiB
C
644 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021, Red Hat, Inc.
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*
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* Tests for Hyper-V features enablement
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*/
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#include <asm/kvm_para.h>
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#include <linux/kvm_para.h>
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#include <stdint.h>
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#include "test_util.h"
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#include "kvm_util.h"
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#include "processor.h"
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#include "hyperv.h"
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#define LINUX_OS_ID ((u64)0x8100 << 48)
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static inline uint8_t hypercall(u64 control, vm_vaddr_t input_address,
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vm_vaddr_t output_address, uint64_t *hv_status)
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{
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uint8_t vector;
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/* Note both the hypercall and the "asm safe" clobber r9-r11. */
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asm volatile("mov %[output_address], %%r8\n\t"
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KVM_ASM_SAFE("vmcall")
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: "=a" (*hv_status),
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"+c" (control), "+d" (input_address),
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KVM_ASM_SAFE_OUTPUTS(vector)
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: [output_address] "r"(output_address),
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"a" (-EFAULT)
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: "cc", "memory", "r8", KVM_ASM_SAFE_CLOBBERS);
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return vector;
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}
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struct msr_data {
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uint32_t idx;
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bool available;
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bool write;
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u64 write_val;
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};
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struct hcall_data {
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uint64_t control;
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uint64_t expect;
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bool ud_expected;
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};
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static void guest_msr(struct msr_data *msr)
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{
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uint64_t ignored;
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uint8_t vector;
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GUEST_ASSERT(msr->idx);
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if (!msr->write)
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vector = rdmsr_safe(msr->idx, &ignored);
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else
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vector = wrmsr_safe(msr->idx, msr->write_val);
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if (msr->available)
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GUEST_ASSERT_2(!vector, msr->idx, vector);
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else
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GUEST_ASSERT_2(vector == GP_VECTOR, msr->idx, vector);
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GUEST_DONE();
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}
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static void guest_hcall(vm_vaddr_t pgs_gpa, struct hcall_data *hcall)
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{
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u64 res, input, output;
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uint8_t vector;
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GUEST_ASSERT(hcall->control);
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wrmsr(HV_X64_MSR_GUEST_OS_ID, LINUX_OS_ID);
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wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa);
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if (!(hcall->control & HV_HYPERCALL_FAST_BIT)) {
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input = pgs_gpa;
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output = pgs_gpa + 4096;
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} else {
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input = output = 0;
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}
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vector = hypercall(hcall->control, input, output, &res);
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if (hcall->ud_expected) {
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GUEST_ASSERT_2(vector == UD_VECTOR, hcall->control, vector);
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} else {
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GUEST_ASSERT_2(!vector, hcall->control, vector);
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GUEST_ASSERT_2(res == hcall->expect, hcall->expect, res);
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}
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GUEST_DONE();
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}
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static void vcpu_reset_hv_cpuid(struct kvm_vcpu *vcpu)
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{
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/*
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* Enable all supported Hyper-V features, then clear the leafs holding
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* the features that will be tested one by one.
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*/
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vcpu_set_hv_cpuid(vcpu);
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vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_FEATURES);
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vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_ENLIGHTMENT_INFO);
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vcpu_clear_cpuid_entry(vcpu, HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
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}
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static void guest_test_msrs_access(void)
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{
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struct kvm_cpuid2 *prev_cpuid = NULL;
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struct kvm_cpuid_entry2 *feat, *dbg;
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struct kvm_vcpu *vcpu;
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struct kvm_run *run;
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struct kvm_vm *vm;
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struct ucall uc;
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int stage = 0;
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vm_vaddr_t msr_gva;
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struct msr_data *msr;
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while (true) {
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vm = vm_create_with_one_vcpu(&vcpu, guest_msr);
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msr_gva = vm_vaddr_alloc_page(vm);
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memset(addr_gva2hva(vm, msr_gva), 0x0, getpagesize());
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msr = addr_gva2hva(vm, msr_gva);
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vcpu_args_set(vcpu, 1, msr_gva);
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vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENFORCE_CPUID, 1);
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if (!prev_cpuid) {
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vcpu_reset_hv_cpuid(vcpu);
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prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent);
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} else {
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vcpu_init_cpuid(vcpu, prev_cpuid);
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}
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feat = vcpu_get_cpuid_entry(vcpu, HYPERV_CPUID_FEATURES);
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dbg = vcpu_get_cpuid_entry(vcpu, HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
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vm_init_descriptor_tables(vm);
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vcpu_init_descriptor_tables(vcpu);
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run = vcpu->run;
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/* TODO: Make this entire test easier to maintain. */
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if (stage >= 21)
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vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_SYNIC2, 0);
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switch (stage) {
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case 0:
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/*
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* Only available when Hyper-V identification is set
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*/
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msr->idx = HV_X64_MSR_GUEST_OS_ID;
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msr->write = 0;
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msr->available = 0;
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break;
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case 1:
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msr->idx = HV_X64_MSR_HYPERCALL;
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msr->write = 0;
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msr->available = 0;
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break;
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case 2:
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feat->eax |= HV_MSR_HYPERCALL_AVAILABLE;
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/*
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* HV_X64_MSR_GUEST_OS_ID has to be written first to make
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* HV_X64_MSR_HYPERCALL available.
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*/
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msr->idx = HV_X64_MSR_GUEST_OS_ID;
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msr->write = 1;
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msr->write_val = LINUX_OS_ID;
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msr->available = 1;
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break;
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case 3:
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msr->idx = HV_X64_MSR_GUEST_OS_ID;
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msr->write = 0;
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msr->available = 1;
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break;
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case 4:
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msr->idx = HV_X64_MSR_HYPERCALL;
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msr->write = 0;
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msr->available = 1;
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break;
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case 5:
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msr->idx = HV_X64_MSR_VP_RUNTIME;
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msr->write = 0;
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msr->available = 0;
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break;
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case 6:
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feat->eax |= HV_MSR_VP_RUNTIME_AVAILABLE;
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msr->idx = HV_X64_MSR_VP_RUNTIME;
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msr->write = 0;
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msr->available = 1;
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break;
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case 7:
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/* Read only */
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msr->idx = HV_X64_MSR_VP_RUNTIME;
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msr->write = 1;
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msr->write_val = 1;
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msr->available = 0;
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break;
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case 8:
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msr->idx = HV_X64_MSR_TIME_REF_COUNT;
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msr->write = 0;
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msr->available = 0;
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break;
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case 9:
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feat->eax |= HV_MSR_TIME_REF_COUNT_AVAILABLE;
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msr->idx = HV_X64_MSR_TIME_REF_COUNT;
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msr->write = 0;
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msr->available = 1;
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break;
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case 10:
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/* Read only */
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msr->idx = HV_X64_MSR_TIME_REF_COUNT;
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msr->write = 1;
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msr->write_val = 1;
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msr->available = 0;
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break;
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case 11:
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msr->idx = HV_X64_MSR_VP_INDEX;
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msr->write = 0;
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msr->available = 0;
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break;
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case 12:
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feat->eax |= HV_MSR_VP_INDEX_AVAILABLE;
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msr->idx = HV_X64_MSR_VP_INDEX;
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msr->write = 0;
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msr->available = 1;
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break;
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case 13:
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/* Read only */
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msr->idx = HV_X64_MSR_VP_INDEX;
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msr->write = 1;
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msr->write_val = 1;
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msr->available = 0;
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break;
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case 14:
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msr->idx = HV_X64_MSR_RESET;
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msr->write = 0;
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msr->available = 0;
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break;
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case 15:
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feat->eax |= HV_MSR_RESET_AVAILABLE;
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msr->idx = HV_X64_MSR_RESET;
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msr->write = 0;
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msr->available = 1;
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break;
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case 16:
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msr->idx = HV_X64_MSR_RESET;
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msr->write = 1;
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msr->write_val = 0;
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msr->available = 1;
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break;
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case 17:
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msr->idx = HV_X64_MSR_REFERENCE_TSC;
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msr->write = 0;
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msr->available = 0;
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break;
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case 18:
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feat->eax |= HV_MSR_REFERENCE_TSC_AVAILABLE;
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msr->idx = HV_X64_MSR_REFERENCE_TSC;
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msr->write = 0;
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msr->available = 1;
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break;
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case 19:
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msr->idx = HV_X64_MSR_REFERENCE_TSC;
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msr->write = 1;
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msr->write_val = 0;
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msr->available = 1;
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break;
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case 20:
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msr->idx = HV_X64_MSR_EOM;
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msr->write = 0;
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msr->available = 0;
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break;
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case 21:
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/*
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* Remains unavailable even with KVM_CAP_HYPERV_SYNIC2
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* capability enabled and guest visible CPUID bit unset.
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*/
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msr->idx = HV_X64_MSR_EOM;
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msr->write = 0;
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msr->available = 0;
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break;
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case 22:
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feat->eax |= HV_MSR_SYNIC_AVAILABLE;
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msr->idx = HV_X64_MSR_EOM;
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msr->write = 0;
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msr->available = 1;
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break;
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case 23:
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msr->idx = HV_X64_MSR_EOM;
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msr->write = 1;
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msr->write_val = 0;
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msr->available = 1;
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break;
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case 24:
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msr->idx = HV_X64_MSR_STIMER0_CONFIG;
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msr->write = 0;
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msr->available = 0;
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break;
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case 25:
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feat->eax |= HV_MSR_SYNTIMER_AVAILABLE;
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msr->idx = HV_X64_MSR_STIMER0_CONFIG;
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msr->write = 0;
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msr->available = 1;
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break;
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case 26:
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msr->idx = HV_X64_MSR_STIMER0_CONFIG;
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msr->write = 1;
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msr->write_val = 0;
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msr->available = 1;
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break;
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case 27:
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/* Direct mode test */
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msr->idx = HV_X64_MSR_STIMER0_CONFIG;
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msr->write = 1;
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msr->write_val = 1 << 12;
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msr->available = 0;
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break;
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case 28:
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feat->edx |= HV_STIMER_DIRECT_MODE_AVAILABLE;
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msr->idx = HV_X64_MSR_STIMER0_CONFIG;
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msr->write = 1;
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msr->write_val = 1 << 12;
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msr->available = 1;
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break;
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case 29:
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msr->idx = HV_X64_MSR_EOI;
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msr->write = 0;
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msr->available = 0;
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break;
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case 30:
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feat->eax |= HV_MSR_APIC_ACCESS_AVAILABLE;
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msr->idx = HV_X64_MSR_EOI;
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msr->write = 1;
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msr->write_val = 1;
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msr->available = 1;
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break;
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case 31:
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msr->idx = HV_X64_MSR_TSC_FREQUENCY;
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msr->write = 0;
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msr->available = 0;
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break;
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case 32:
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feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
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msr->idx = HV_X64_MSR_TSC_FREQUENCY;
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msr->write = 0;
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msr->available = 1;
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break;
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case 33:
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/* Read only */
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msr->idx = HV_X64_MSR_TSC_FREQUENCY;
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msr->write = 1;
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msr->write_val = 1;
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msr->available = 0;
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break;
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case 34:
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|
|
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 0;
|
||
|
|
break;
|
||
|
|
case 35:
|
||
|
|
feat->eax |= HV_ACCESS_REENLIGHTENMENT;
|
||
|
|
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
case 36:
|
||
|
|
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
|
||
|
|
msr->write = 1;
|
||
|
|
msr->write_val = 1;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
case 37:
|
||
|
|
/* Can only write '0' */
|
||
|
|
msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS;
|
||
|
|
msr->write = 1;
|
||
|
|
msr->write_val = 1;
|
||
|
|
msr->available = 0;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 38:
|
||
|
|
msr->idx = HV_X64_MSR_CRASH_P0;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 0;
|
||
|
|
break;
|
||
|
|
case 39:
|
||
|
|
feat->edx |= HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE;
|
||
|
|
msr->idx = HV_X64_MSR_CRASH_P0;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
case 40:
|
||
|
|
msr->idx = HV_X64_MSR_CRASH_P0;
|
||
|
|
msr->write = 1;
|
||
|
|
msr->write_val = 1;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 41:
|
||
|
|
msr->idx = HV_X64_MSR_SYNDBG_STATUS;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 0;
|
||
|
|
break;
|
||
|
|
case 42:
|
||
|
|
feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
|
||
|
|
dbg->eax |= HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
|
||
|
|
msr->idx = HV_X64_MSR_SYNDBG_STATUS;
|
||
|
|
msr->write = 0;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
case 43:
|
||
|
|
msr->idx = HV_X64_MSR_SYNDBG_STATUS;
|
||
|
|
msr->write = 1;
|
||
|
|
msr->write_val = 0;
|
||
|
|
msr->available = 1;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 44:
|
||
|
|
kvm_vm_free(vm);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
vcpu_set_cpuid(vcpu);
|
||
|
|
|
||
|
|
memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent));
|
||
|
|
|
||
|
|
pr_debug("Stage %d: testing msr: 0x%x for %s\n", stage,
|
||
|
|
msr->idx, msr->write ? "write" : "read");
|
||
|
|
|
||
|
|
vcpu_run(vcpu);
|
||
|
|
TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,
|
||
|
|
"unexpected exit reason: %u (%s)",
|
||
|
|
run->exit_reason, exit_reason_str(run->exit_reason));
|
||
|
|
|
||
|
|
switch (get_ucall(vcpu, &uc)) {
|
||
|
|
case UCALL_ABORT:
|
||
|
|
REPORT_GUEST_ASSERT_2(uc, "MSR = %lx, vector = %lx");
|
||
|
|
return;
|
||
|
|
case UCALL_DONE:
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
TEST_FAIL("Unhandled ucall: %ld", uc.cmd);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
stage++;
|
||
|
|
kvm_vm_free(vm);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void guest_test_hcalls_access(void)
|
||
|
|
{
|
||
|
|
struct kvm_cpuid_entry2 *feat, *recomm, *dbg;
|
||
|
|
struct kvm_cpuid2 *prev_cpuid = NULL;
|
||
|
|
struct kvm_vcpu *vcpu;
|
||
|
|
struct kvm_run *run;
|
||
|
|
struct kvm_vm *vm;
|
||
|
|
struct ucall uc;
|
||
|
|
int stage = 0;
|
||
|
|
vm_vaddr_t hcall_page, hcall_params;
|
||
|
|
struct hcall_data *hcall;
|
||
|
|
|
||
|
|
while (true) {
|
||
|
|
vm = vm_create_with_one_vcpu(&vcpu, guest_hcall);
|
||
|
|
|
||
|
|
vm_init_descriptor_tables(vm);
|
||
|
|
vcpu_init_descriptor_tables(vcpu);
|
||
|
|
|
||
|
|
/* Hypercall input/output */
|
||
|
|
hcall_page = vm_vaddr_alloc_pages(vm, 2);
|
||
|
|
memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize());
|
||
|
|
|
||
|
|
hcall_params = vm_vaddr_alloc_page(vm);
|
||
|
|
memset(addr_gva2hva(vm, hcall_params), 0x0, getpagesize());
|
||
|
|
hcall = addr_gva2hva(vm, hcall_params);
|
||
|
|
|
||
|
|
vcpu_args_set(vcpu, 2, addr_gva2gpa(vm, hcall_page), hcall_params);
|
||
|
|
vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENFORCE_CPUID, 1);
|
||
|
|
|
||
|
|
if (!prev_cpuid) {
|
||
|
|
vcpu_reset_hv_cpuid(vcpu);
|
||
|
|
|
||
|
|
prev_cpuid = allocate_kvm_cpuid2(vcpu->cpuid->nent);
|
||
|
|
} else {
|
||
|
|
vcpu_init_cpuid(vcpu, prev_cpuid);
|
||
|
|
}
|
||
|
|
|
||
|
|
feat = vcpu_get_cpuid_entry(vcpu, HYPERV_CPUID_FEATURES);
|
||
|
|
recomm = vcpu_get_cpuid_entry(vcpu, HYPERV_CPUID_ENLIGHTMENT_INFO);
|
||
|
|
dbg = vcpu_get_cpuid_entry(vcpu, HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
|
||
|
|
|
||
|
|
run = vcpu->run;
|
||
|
|
|
||
|
|
switch (stage) {
|
||
|
|
case 0:
|
||
|
|
feat->eax |= HV_MSR_HYPERCALL_AVAILABLE;
|
||
|
|
hcall->control = 0xbeef;
|
||
|
|
hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 1:
|
||
|
|
hcall->control = HVCALL_POST_MESSAGE;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
feat->ebx |= HV_POST_MESSAGES;
|
||
|
|
hcall->control = HVCALL_POST_MESSAGE;
|
||
|
|
hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 3:
|
||
|
|
hcall->control = HVCALL_SIGNAL_EVENT;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
feat->ebx |= HV_SIGNAL_EVENTS;
|
||
|
|
hcall->control = HVCALL_SIGNAL_EVENT;
|
||
|
|
hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 5:
|
||
|
|
hcall->control = HVCALL_RESET_DEBUG_SESSION;
|
||
|
|
hcall->expect = HV_STATUS_INVALID_HYPERCALL_CODE;
|
||
|
|
break;
|
||
|
|
case 6:
|
||
|
|
dbg->eax |= HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
|
||
|
|
hcall->control = HVCALL_RESET_DEBUG_SESSION;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 7:
|
||
|
|
feat->ebx |= HV_DEBUGGING;
|
||
|
|
hcall->control = HVCALL_RESET_DEBUG_SESSION;
|
||
|
|
hcall->expect = HV_STATUS_OPERATION_DENIED;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 8:
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 9:
|
||
|
|
recomm->eax |= HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED;
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE;
|
||
|
|
hcall->expect = HV_STATUS_SUCCESS;
|
||
|
|
break;
|
||
|
|
case 10:
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 11:
|
||
|
|
recomm->eax |= HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED;
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX;
|
||
|
|
hcall->expect = HV_STATUS_SUCCESS;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 12:
|
||
|
|
hcall->control = HVCALL_SEND_IPI;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 13:
|
||
|
|
recomm->eax |= HV_X64_CLUSTER_IPI_RECOMMENDED;
|
||
|
|
hcall->control = HVCALL_SEND_IPI;
|
||
|
|
hcall->expect = HV_STATUS_INVALID_HYPERCALL_INPUT;
|
||
|
|
break;
|
||
|
|
case 14:
|
||
|
|
/* Nothing in 'sparse banks' -> success */
|
||
|
|
hcall->control = HVCALL_SEND_IPI_EX;
|
||
|
|
hcall->expect = HV_STATUS_SUCCESS;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case 15:
|
||
|
|
hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT;
|
||
|
|
hcall->expect = HV_STATUS_ACCESS_DENIED;
|
||
|
|
break;
|
||
|
|
case 16:
|
||
|
|
recomm->ebx = 0xfff;
|
||
|
|
hcall->control = HVCALL_NOTIFY_LONG_SPIN_WAIT;
|
||
|
|
hcall->expect = HV_STATUS_SUCCESS;
|
||
|
|
break;
|
||
|
|
case 17:
|
||
|
|
/* XMM fast hypercall */
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT;
|
||
|
|
hcall->ud_expected = true;
|
||
|
|
break;
|
||
|
|
case 18:
|
||
|
|
feat->edx |= HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE;
|
||
|
|
hcall->control = HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE | HV_HYPERCALL_FAST_BIT;
|
||
|
|
hcall->ud_expected = false;
|
||
|
|
hcall->expect = HV_STATUS_SUCCESS;
|
||
|
|
break;
|
||
|
|
case 19:
|
||
|
|
kvm_vm_free(vm);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
vcpu_set_cpuid(vcpu);
|
||
|
|
|
||
|
|
memcpy(prev_cpuid, vcpu->cpuid, kvm_cpuid2_size(vcpu->cpuid->nent));
|
||
|
|
|
||
|
|
pr_debug("Stage %d: testing hcall: 0x%lx\n", stage, hcall->control);
|
||
|
|
|
||
|
|
vcpu_run(vcpu);
|
||
|
|
TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,
|
||
|
|
"unexpected exit reason: %u (%s)",
|
||
|
|
run->exit_reason, exit_reason_str(run->exit_reason));
|
||
|
|
|
||
|
|
switch (get_ucall(vcpu, &uc)) {
|
||
|
|
case UCALL_ABORT:
|
||
|
|
REPORT_GUEST_ASSERT_2(uc, "arg1 = %lx, arg2 = %lx");
|
||
|
|
return;
|
||
|
|
case UCALL_DONE:
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
TEST_FAIL("Unhandled ucall: %ld", uc.cmd);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
stage++;
|
||
|
|
kvm_vm_free(vm);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int main(void)
|
||
|
|
{
|
||
|
|
pr_info("Testing access to Hyper-V specific MSRs\n");
|
||
|
|
guest_test_msrs_access();
|
||
|
|
|
||
|
|
pr_info("Testing access to Hyper-V hypercalls\n");
|
||
|
|
guest_test_hcalls_access();
|
||
|
|
}
|