240 lines
7.4 KiB
C
240 lines
7.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* NAU85L40 ALSA SoC audio driver
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*
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* Copyright 2016 Nuvoton Technology Corp.
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* Author: John Hsu <KCHSU0@nuvoton.com>
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*/
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#ifndef __NAU8540_H__
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#define __NAU8540_H__
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#define NAU8540_REG_SW_RESET 0x00
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#define NAU8540_REG_POWER_MANAGEMENT 0x01
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#define NAU8540_REG_CLOCK_CTRL 0x02
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#define NAU8540_REG_CLOCK_SRC 0x03
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#define NAU8540_REG_FLL1 0x04
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#define NAU8540_REG_FLL2 0x05
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#define NAU8540_REG_FLL3 0x06
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#define NAU8540_REG_FLL4 0x07
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#define NAU8540_REG_FLL5 0x08
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#define NAU8540_REG_FLL6 0x09
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#define NAU8540_REG_FLL_VCO_RSV 0x0A
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#define NAU8540_REG_PCM_CTRL0 0x10
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#define NAU8540_REG_PCM_CTRL1 0x11
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#define NAU8540_REG_PCM_CTRL2 0x12
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#define NAU8540_REG_PCM_CTRL3 0x13
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#define NAU8540_REG_PCM_CTRL4 0x14
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#define NAU8540_REG_ALC_CONTROL_1 0x20
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#define NAU8540_REG_ALC_CONTROL_2 0x21
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#define NAU8540_REG_ALC_CONTROL_3 0x22
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#define NAU8540_REG_ALC_CONTROL_4 0x23
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#define NAU8540_REG_ALC_CONTROL_5 0x24
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#define NAU8540_REG_ALC_GAIN_CH12 0x2D
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#define NAU8540_REG_ALC_GAIN_CH34 0x2E
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#define NAU8540_REG_ALC_STATUS 0x2F
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#define NAU8540_REG_NOTCH_FIL1_CH1 0x30
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#define NAU8540_REG_NOTCH_FIL2_CH1 0x31
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#define NAU8540_REG_NOTCH_FIL1_CH2 0x32
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#define NAU8540_REG_NOTCH_FIL2_CH2 0x33
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#define NAU8540_REG_NOTCH_FIL1_CH3 0x34
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#define NAU8540_REG_NOTCH_FIL2_CH3 0x35
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#define NAU8540_REG_NOTCH_FIL1_CH4 0x36
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#define NAU8540_REG_NOTCH_FIL2_CH4 0x37
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#define NAU8540_REG_HPF_FILTER_CH12 0x38
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#define NAU8540_REG_HPF_FILTER_CH34 0x39
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#define NAU8540_REG_ADC_SAMPLE_RATE 0x3A
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#define NAU8540_REG_DIGITAL_GAIN_CH1 0x40
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#define NAU8540_REG_DIGITAL_GAIN_CH2 0x41
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#define NAU8540_REG_DIGITAL_GAIN_CH3 0x42
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#define NAU8540_REG_DIGITAL_GAIN_CH4 0x43
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#define NAU8540_REG_DIGITAL_MUX 0x44
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#define NAU8540_REG_P2P_CH1 0x48
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#define NAU8540_REG_P2P_CH2 0x49
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#define NAU8540_REG_P2P_CH3 0x4A
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#define NAU8540_REG_P2P_CH4 0x4B
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#define NAU8540_REG_PEAK_CH1 0x4C
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#define NAU8540_REG_PEAK_CH2 0x4D
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#define NAU8540_REG_PEAK_CH3 0x4E
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#define NAU8540_REG_PEAK_CH4 0x4F
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#define NAU8540_REG_GPIO_CTRL 0x50
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#define NAU8540_REG_MISC_CTRL 0x51
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#define NAU8540_REG_I2C_CTRL 0x52
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#define NAU8540_REG_I2C_DEVICE_ID 0x58
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#define NAU8540_REG_RST 0x5A
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#define NAU8540_REG_VMID_CTRL 0x60
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#define NAU8540_REG_MUTE 0x61
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#define NAU8540_REG_ANALOG_ADC1 0x64
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#define NAU8540_REG_ANALOG_ADC2 0x65
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#define NAU8540_REG_ANALOG_PWR 0x66
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#define NAU8540_REG_MIC_BIAS 0x67
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#define NAU8540_REG_REFERENCE 0x68
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#define NAU8540_REG_FEPGA1 0x69
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#define NAU8540_REG_FEPGA2 0x6A
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#define NAU8540_REG_FEPGA3 0x6B
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#define NAU8540_REG_FEPGA4 0x6C
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#define NAU8540_REG_PWR 0x6D
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#define NAU8540_REG_MAX NAU8540_REG_PWR
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/* POWER_MANAGEMENT (0x01) */
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#define NAU8540_ADC4_EN (0x1 << 3)
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#define NAU8540_ADC3_EN (0x1 << 2)
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#define NAU8540_ADC2_EN (0x1 << 1)
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#define NAU8540_ADC1_EN 0x1
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/* CLOCK_CTRL (0x02) */
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#define NAU8540_CLK_ADC_EN (0x1 << 15)
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#define NAU8540_CLK_I2S_EN (0x1 << 1)
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/* CLOCK_SRC (0x03) */
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#define NAU8540_CLK_SRC_SFT 15
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#define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT)
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#define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT)
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#define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT)
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#define NAU8540_CLK_ADC_SRC_SFT 6
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#define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)
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#define NAU8540_CLK_MCLK_SRC_MASK 0xf
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/* FLL1 (0x04) */
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#define NAU8540_ICTRL_LATCH_SFT 10
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#define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT)
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#define NAU8540_FLL_RATIO_MASK 0x7f
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/* FLL3 (0x06) */
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#define NAU8540_GAIN_ERR_SFT 12
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#define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT)
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#define NAU8540_FLL_CLK_SRC_SFT 10
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#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
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#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
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#define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
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#define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)
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#define NAU8540_FLL_INTEGER_MASK 0x3ff
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/* FLL4 (0x07) */
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#define NAU8540_FLL_REF_DIV_SFT 10
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#define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)
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/* FLL5 (0x08) */
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#define NAU8540_FLL_PDB_DAC_EN (0x1 << 15)
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#define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
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#define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
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#define NAU8540_FLL_CLK_SW_N2 (0x1 << 13)
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#define NAU8540_FLL_CLK_SW_REF (0x0 << 13)
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#define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
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#define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
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#define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12)
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/* FLL6 (0x9) */
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#define NAU8540_DCO_EN (0x1 << 15)
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#define NAU8540_SDM_EN (0x1 << 14)
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#define NAU8540_CUTOFF500 (0x1 << 13)
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/* PCM_CTRL0 (0x10) */
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#define NAU8540_I2S_BP_SFT 7
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#define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT)
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#define NAU8540_I2S_PCMB_SFT 6
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#define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT)
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#define NAU8540_I2S_DL_SFT 2
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#define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)
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#define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT)
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#define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT)
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#define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT)
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#define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)
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#define NAU8540_I2S_DF_MASK 0x3
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#define NAU8540_I2S_DF_RIGTH 0
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#define NAU8540_I2S_DF_LEFT 0x1
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#define NAU8540_I2S_DF_I2S 0x2
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#define NAU8540_I2S_DF_PCM_AB 0x3
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/* PCM_CTRL1 (0x11) */
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#define NAU8540_I2S_DO12_TRI (0x1 << 15)
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#define NAU8540_I2S_LRC_DIV_SFT 12
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#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
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#define NAU8540_I2S_DO12_OE (0x1 << 4)
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#define NAU8540_I2S_MS_SFT 3
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#define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT)
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#define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT)
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#define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT)
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#define NAU8540_I2S_BLK_DIV_MASK 0x7
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/* PCM_CTRL1 (0x12) */
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#define NAU8540_I2S_DO34_TRI (0x1 << 15)
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#define NAU8540_I2S_DO34_OE (0x1 << 11)
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#define NAU8540_I2S_TSLOT_L_MASK 0x3ff
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/* PCM_CTRL4 (0x14) */
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#define NAU8540_TDM_MODE (0x1 << 15)
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#define NAU8540_TDM_OFFSET_EN (0x1 << 14)
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#define NAU8540_TDM_TX_MASK 0xf
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/* ADC_SAMPLE_RATE (0x3A) */
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#define NAU8540_CH_SYNC (0x1 << 14)
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#define NAU8540_ADC_OSR_MASK 0x3
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#define NAU8540_ADC_OSR_256 0x3
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#define NAU8540_ADC_OSR_128 0x2
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#define NAU8540_ADC_OSR_64 0x1
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#define NAU8540_ADC_OSR_32 0x0
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/* VMID_CTRL (0x60) */
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#define NAU8540_VMID_EN (1 << 6)
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#define NAU8540_VMID_SEL_SFT 4
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#define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT)
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/* MIC_BIAS (0x67) */
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#define NAU8540_PU_PRE (0x1 << 8)
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/* REFERENCE (0x68) */
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#define NAU8540_PRECHARGE_DIS (0x1 << 13)
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#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
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/* FEPGA1 (0x69) */
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#define NAU8540_FEPGA1_MODCH2_SHT_SFT 7
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#define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
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#define NAU8540_FEPGA1_MODCH1_SHT_SFT 3
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#define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
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/* FEPGA2 (0x6A) */
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#define NAU8540_FEPGA2_MODCH4_SHT_SFT 7
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#define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
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#define NAU8540_FEPGA2_MODCH3_SHT_SFT 3
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#define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
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/* System Clock Source */
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enum {
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NAU8540_CLK_DIS,
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NAU8540_CLK_MCLK,
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NAU8540_CLK_INTERNAL,
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NAU8540_CLK_FLL_MCLK,
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NAU8540_CLK_FLL_BLK,
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NAU8540_CLK_FLL_FS,
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};
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struct nau8540 {
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struct device *dev;
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struct regmap *regmap;
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};
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struct nau8540_fll {
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int mclk_src;
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int ratio;
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int fll_frac;
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int fll_int;
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int clk_ref_div;
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};
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struct nau8540_fll_attr {
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unsigned int param;
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unsigned int val;
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};
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/* over sampling rate */
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struct nau8540_osr_attr {
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unsigned int osr;
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unsigned int clk_src;
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};
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#endif /* __NAU8540_H__ */
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