437 lines
11 KiB
C
437 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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#include <dt-bindings/power/fsl,imx93-power.h>
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#define BLK_SFT_RSTN 0x0
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#define BLK_CLK_EN 0x4
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#define BLK_MAX_CLKS 4
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#define DOMAIN_MAX_CLKS 4
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#define LCDIF_QOS_REG 0xC
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#define LCDIF_DEFAULT_QOS_OFF 12
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#define LCDIF_CFG_QOS_OFF 8
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#define PXP_QOS_REG 0x10
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#define PXP_R_DEFAULT_QOS_OFF 28
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#define PXP_R_CFG_QOS_OFF 24
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#define PXP_W_DEFAULT_QOS_OFF 20
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#define PXP_W_CFG_QOS_OFF 16
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#define ISI_CACHE_REG 0x14
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#define ISI_QOS_REG 0x1C
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#define ISI_V_DEFAULT_QOS_OFF 28
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#define ISI_V_CFG_QOS_OFF 24
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#define ISI_U_DEFAULT_QOS_OFF 20
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#define ISI_U_CFG_QOS_OFF 16
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#define ISI_Y_R_DEFAULT_QOS_OFF 12
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#define ISI_Y_R_CFG_QOS_OFF 8
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#define ISI_Y_W_DEFAULT_QOS_OFF 4
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#define ISI_Y_W_CFG_QOS_OFF 0
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#define PRIO_MASK 0xF
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#define PRIO(X) (X)
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struct imx93_blk_ctrl_domain;
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struct imx93_blk_ctrl {
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struct device *dev;
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struct regmap *regmap;
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int num_clks;
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struct clk_bulk_data clks[BLK_MAX_CLKS];
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struct imx93_blk_ctrl_domain *domains;
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struct genpd_onecell_data onecell_data;
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};
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#define DOMAIN_MAX_QOS 4
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struct imx93_blk_ctrl_qos {
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u32 reg;
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u32 cfg_off;
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u32 default_prio;
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u32 cfg_prio;
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};
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struct imx93_blk_ctrl_domain_data {
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const char *name;
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const char * const *clk_names;
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int num_clks;
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u32 rst_mask;
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u32 clk_mask;
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int num_qos;
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struct imx93_blk_ctrl_qos qos[DOMAIN_MAX_QOS];
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};
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struct imx93_blk_ctrl_domain {
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struct generic_pm_domain genpd;
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const struct imx93_blk_ctrl_domain_data *data;
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struct clk_bulk_data clks[DOMAIN_MAX_CLKS];
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struct imx93_blk_ctrl *bc;
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};
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struct imx93_blk_ctrl_data {
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const struct imx93_blk_ctrl_domain_data *domains;
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int num_domains;
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const char * const *clk_names;
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int num_clks;
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const struct regmap_access_table *reg_access_table;
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};
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static inline struct imx93_blk_ctrl_domain *
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to_imx93_blk_ctrl_domain(struct generic_pm_domain *genpd)
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{
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return container_of(genpd, struct imx93_blk_ctrl_domain, genpd);
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}
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static int imx93_blk_ctrl_set_qos(struct imx93_blk_ctrl_domain *domain)
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{
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const struct imx93_blk_ctrl_domain_data *data = domain->data;
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struct imx93_blk_ctrl *bc = domain->bc;
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const struct imx93_blk_ctrl_qos *qos;
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u32 val, mask;
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int i;
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for (i = 0; i < data->num_qos; i++) {
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qos = &data->qos[i];
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mask = PRIO_MASK << qos->cfg_off;
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mask |= PRIO_MASK << (qos->cfg_off + 4);
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val = qos->cfg_prio << qos->cfg_off;
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val |= qos->default_prio << (qos->cfg_off + 4);
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regmap_write_bits(bc->regmap, qos->reg, mask, val);
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dev_dbg(bc->dev, "data->qos[i].reg 0x%x 0x%x\n", qos->reg, val);
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}
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return 0;
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}
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static int imx93_blk_ctrl_power_on(struct generic_pm_domain *genpd)
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{
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struct imx93_blk_ctrl_domain *domain = to_imx93_blk_ctrl_domain(genpd);
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const struct imx93_blk_ctrl_domain_data *data = domain->data;
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struct imx93_blk_ctrl *bc = domain->bc;
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int ret;
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ret = clk_bulk_prepare_enable(bc->num_clks, bc->clks);
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if (ret) {
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dev_err(bc->dev, "failed to enable bus clocks\n");
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return ret;
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}
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ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
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if (ret) {
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clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
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dev_err(bc->dev, "failed to enable clocks\n");
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return ret;
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}
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ret = pm_runtime_get_sync(bc->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(bc->dev);
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dev_err(bc->dev, "failed to power up domain\n");
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goto disable_clk;
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}
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/* ungate clk */
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regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
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/* release reset */
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
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dev_dbg(bc->dev, "pd_on: name: %s\n", genpd->name);
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return imx93_blk_ctrl_set_qos(domain);
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disable_clk:
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clk_bulk_disable_unprepare(data->num_clks, domain->clks);
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clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
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return ret;
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}
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static int imx93_blk_ctrl_power_off(struct generic_pm_domain *genpd)
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{
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struct imx93_blk_ctrl_domain *domain = to_imx93_blk_ctrl_domain(genpd);
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const struct imx93_blk_ctrl_domain_data *data = domain->data;
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struct imx93_blk_ctrl *bc = domain->bc;
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dev_dbg(bc->dev, "pd_off: name: %s\n", genpd->name);
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regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);
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regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
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pm_runtime_put(bc->dev);
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clk_bulk_disable_unprepare(data->num_clks, domain->clks);
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clk_bulk_disable_unprepare(bc->num_clks, bc->clks);
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return 0;
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}
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static int imx93_blk_ctrl_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct imx93_blk_ctrl_data *bc_data = of_device_get_match_data(dev);
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struct imx93_blk_ctrl *bc;
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void __iomem *base;
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int i, ret;
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struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.rd_table = bc_data->reg_access_table,
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.wr_table = bc_data->reg_access_table,
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.max_register = SZ_4K,
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};
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bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
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if (!bc)
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return -ENOMEM;
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bc->dev = dev;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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if (IS_ERR(bc->regmap))
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return dev_err_probe(dev, PTR_ERR(bc->regmap),
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"failed to init regmap\n");
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bc->domains = devm_kcalloc(dev, bc_data->num_domains,
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sizeof(struct imx93_blk_ctrl_domain),
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GFP_KERNEL);
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if (!bc->domains)
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return -ENOMEM;
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bc->onecell_data.num_domains = bc_data->num_domains;
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bc->onecell_data.domains =
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devm_kcalloc(dev, bc_data->num_domains,
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sizeof(struct generic_pm_domain *), GFP_KERNEL);
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if (!bc->onecell_data.domains)
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return -ENOMEM;
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for (i = 0; i < bc_data->num_clks; i++)
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bc->clks[i].id = bc_data->clk_names[i];
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bc->num_clks = bc_data->num_clks;
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ret = devm_clk_bulk_get(dev, bc->num_clks, bc->clks);
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if (ret) {
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dev_err_probe(dev, ret, "failed to get bus clock\n");
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return ret;
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}
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for (i = 0; i < bc_data->num_domains; i++) {
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const struct imx93_blk_ctrl_domain_data *data = &bc_data->domains[i];
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struct imx93_blk_ctrl_domain *domain = &bc->domains[i];
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int j;
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domain->data = data;
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for (j = 0; j < data->num_clks; j++)
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domain->clks[j].id = data->clk_names[j];
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ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
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if (ret) {
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dev_err_probe(dev, ret, "failed to get clock\n");
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goto cleanup_pds;
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}
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domain->genpd.name = data->name;
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domain->genpd.power_on = imx93_blk_ctrl_power_on;
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domain->genpd.power_off = imx93_blk_ctrl_power_off;
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domain->bc = bc;
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ret = pm_genpd_init(&domain->genpd, NULL, true);
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if (ret) {
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dev_err_probe(dev, ret, "failed to init power domain\n");
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goto cleanup_pds;
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}
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bc->onecell_data.domains[i] = &domain->genpd;
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}
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pm_runtime_enable(dev);
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ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
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if (ret) {
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dev_err_probe(dev, ret, "failed to add power domain provider\n");
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goto cleanup_pds;
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}
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dev_set_drvdata(dev, bc);
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return 0;
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cleanup_pds:
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for (i--; i >= 0; i--)
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pm_genpd_remove(&bc->domains[i].genpd);
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return ret;
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}
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static int imx93_blk_ctrl_remove(struct platform_device *pdev)
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{
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struct imx93_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
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int i;
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of_genpd_del_provider(pdev->dev.of_node);
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for (i = 0; bc->onecell_data.num_domains; i++) {
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struct imx93_blk_ctrl_domain *domain = &bc->domains[i];
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pm_genpd_remove(&domain->genpd);
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}
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return 0;
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}
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static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_domain_data[] = {
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[IMX93_MEDIABLK_PD_MIPI_DSI] = {
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.name = "mediablk-mipi-dsi",
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.clk_names = (const char *[]){ "dsi" },
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.num_clks = 1,
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.rst_mask = BIT(11) | BIT(12),
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.clk_mask = BIT(11) | BIT(12),
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},
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[IMX93_MEDIABLK_PD_MIPI_CSI] = {
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.name = "mediablk-mipi-csi",
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.clk_names = (const char *[]){ "cam", "csi" },
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.num_clks = 2,
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.rst_mask = BIT(9) | BIT(10),
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.clk_mask = BIT(9) | BIT(10),
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},
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[IMX93_MEDIABLK_PD_PXP] = {
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.name = "mediablk-pxp",
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.clk_names = (const char *[]){ "pxp" },
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.num_clks = 1,
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.rst_mask = BIT(7) | BIT(8),
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.clk_mask = BIT(7) | BIT(8),
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.num_qos = 2,
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.qos = {
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{
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.reg = PXP_QOS_REG,
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.cfg_off = PXP_R_CFG_QOS_OFF,
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.default_prio = PRIO(3),
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.cfg_prio = PRIO(6),
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}, {
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.reg = PXP_QOS_REG,
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.cfg_off = PXP_W_CFG_QOS_OFF,
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.default_prio = PRIO(3),
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.cfg_prio = PRIO(6),
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}
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}
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},
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[IMX93_MEDIABLK_PD_LCDIF] = {
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.name = "mediablk-lcdif",
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.clk_names = (const char *[]){ "disp", "lcdif" },
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.num_clks = 2,
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.rst_mask = BIT(4) | BIT(5) | BIT(6),
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.clk_mask = BIT(4) | BIT(5) | BIT(6),
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.num_qos = 1,
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.qos = {
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{
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.reg = LCDIF_QOS_REG,
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.cfg_off = LCDIF_CFG_QOS_OFF,
|
||
|
|
.default_prio = PRIO(3),
|
||
|
|
.cfg_prio = PRIO(7),
|
||
|
|
}
|
||
|
|
}
|
||
|
|
},
|
||
|
|
[IMX93_MEDIABLK_PD_ISI] = {
|
||
|
|
.name = "mediablk-isi",
|
||
|
|
.clk_names = (const char *[]){ "isi" },
|
||
|
|
.num_clks = 1,
|
||
|
|
.rst_mask = BIT(2) | BIT(3),
|
||
|
|
.clk_mask = BIT(2) | BIT(3),
|
||
|
|
.num_qos = 4,
|
||
|
|
.qos = {
|
||
|
|
{
|
||
|
|
.reg = ISI_QOS_REG,
|
||
|
|
.cfg_off = ISI_Y_W_CFG_QOS_OFF,
|
||
|
|
.default_prio = PRIO(3),
|
||
|
|
.cfg_prio = PRIO(7),
|
||
|
|
}, {
|
||
|
|
.reg = ISI_QOS_REG,
|
||
|
|
.cfg_off = ISI_Y_R_CFG_QOS_OFF,
|
||
|
|
.default_prio = PRIO(3),
|
||
|
|
.cfg_prio = PRIO(7),
|
||
|
|
}, {
|
||
|
|
.reg = ISI_QOS_REG,
|
||
|
|
.cfg_off = ISI_U_CFG_QOS_OFF,
|
||
|
|
.default_prio = PRIO(3),
|
||
|
|
.cfg_prio = PRIO(7),
|
||
|
|
}, {
|
||
|
|
.reg = ISI_QOS_REG,
|
||
|
|
.cfg_off = ISI_V_CFG_QOS_OFF,
|
||
|
|
.default_prio = PRIO(3),
|
||
|
|
.cfg_prio = PRIO(7),
|
||
|
|
}
|
||
|
|
}
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_range imx93_media_blk_ctl_yes_ranges[] = {
|
||
|
|
regmap_reg_range(BLK_SFT_RSTN, BLK_CLK_EN),
|
||
|
|
regmap_reg_range(LCDIF_QOS_REG, ISI_CACHE_REG),
|
||
|
|
regmap_reg_range(ISI_QOS_REG, ISI_QOS_REG),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_access_table imx93_media_blk_ctl_access_table = {
|
||
|
|
.yes_ranges = imx93_media_blk_ctl_yes_ranges,
|
||
|
|
.n_yes_ranges = ARRAY_SIZE(imx93_media_blk_ctl_yes_ranges),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = {
|
||
|
|
.domains = imx93_media_blk_ctl_domain_data,
|
||
|
|
.num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data),
|
||
|
|
.clk_names = (const char *[]){ "axi", "apb", "nic", },
|
||
|
|
.num_clks = 3,
|
||
|
|
.reg_access_table = &imx93_media_blk_ctl_access_table,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id imx93_blk_ctrl_of_match[] = {
|
||
|
|
{
|
||
|
|
.compatible = "fsl,imx93-media-blk-ctrl",
|
||
|
|
.data = &imx93_media_blk_ctl_dev_data
|
||
|
|
}, {
|
||
|
|
/* Sentinel */
|
||
|
|
}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, imx93_blk_ctrl_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver imx93_blk_ctrl_driver = {
|
||
|
|
.probe = imx93_blk_ctrl_probe,
|
||
|
|
.remove = imx93_blk_ctrl_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "imx93-blk-ctrl",
|
||
|
|
.of_match_table = imx93_blk_ctrl_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(imx93_blk_ctrl_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
|
||
|
|
MODULE_DESCRIPTION("i.MX93 BLK CTRL driver");
|
||
|
|
MODULE_LICENSE("GPL");
|