454 lines
11 KiB
C
454 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe endpoint controller driver for UniPhier SoCs
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* Copyright 2018 Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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/* Link Glue registers */
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#define PCL_RSTCTRL0 0x0010
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#define PCL_RSTCTRL_AXI_REG BIT(3)
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#define PCL_RSTCTRL_AXI_SLAVE BIT(2)
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#define PCL_RSTCTRL_AXI_MASTER BIT(1)
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#define PCL_RSTCTRL_PIPE3 BIT(0)
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#define PCL_RSTCTRL1 0x0020
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#define PCL_RSTCTRL_PERST BIT(0)
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#define PCL_RSTCTRL2 0x0024
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#define PCL_RSTCTRL_PHY_RESET BIT(0)
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#define PCL_PINCTRL0 0x002c
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#define PCL_PERST_PLDN_REGEN BIT(12)
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#define PCL_PERST_NOE_REGEN BIT(11)
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#define PCL_PERST_OUT_REGEN BIT(8)
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#define PCL_PERST_PLDN_REGVAL BIT(4)
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#define PCL_PERST_NOE_REGVAL BIT(3)
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#define PCL_PERST_OUT_REGVAL BIT(0)
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#define PCL_PIPEMON 0x0044
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#define PCL_PCLK_ALIVE BIT(15)
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#define PCL_MODE 0x8000
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#define PCL_MODE_REGEN BIT(8)
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#define PCL_MODE_REGVAL BIT(0)
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#define PCL_APP_CLK_CTRL 0x8004
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#define PCL_APP_CLK_REQ BIT(0)
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#define PCL_APP_READY_CTRL 0x8008
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#define PCL_APP_LTSSM_ENABLE BIT(0)
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#define PCL_APP_MSI0 0x8040
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#define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8)
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#define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0)
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#define PCL_APP_MSI1 0x8044
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#define PCL_APP_MSI_REQ BIT(0)
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#define PCL_APP_INTX 0x8074
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#define PCL_APP_INTX_SYS_INT BIT(0)
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#define PCL_APP_PM0 0x8078
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#define PCL_SYS_AUX_PWR_DET BIT(8)
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/* assertion time of INTx in usec */
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#define PCL_INTX_WIDTH_USEC 30
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struct uniphier_pcie_ep_priv {
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void __iomem *base;
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struct dw_pcie pci;
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struct clk *clk, *clk_gio;
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struct reset_control *rst, *rst_gio;
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struct phy *phy;
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const struct uniphier_pcie_ep_soc_data *data;
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};
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struct uniphier_pcie_ep_soc_data {
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bool has_gio;
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void (*init)(struct uniphier_pcie_ep_priv *priv);
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int (*wait)(struct uniphier_pcie_ep_priv *priv);
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const struct pci_epc_features features;
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};
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#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
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static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv,
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bool enable)
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{
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u32 val;
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val = readl(priv->base + PCL_APP_READY_CTRL);
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if (enable)
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val |= PCL_APP_LTSSM_ENABLE;
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else
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val &= ~PCL_APP_LTSSM_ENABLE;
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writel(val, priv->base + PCL_APP_READY_CTRL);
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}
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static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
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bool assert)
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{
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u32 val;
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val = readl(priv->base + PCL_RSTCTRL2);
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if (assert)
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val |= PCL_RSTCTRL_PHY_RESET;
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else
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val &= ~PCL_RSTCTRL_PHY_RESET;
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writel(val, priv->base + PCL_RSTCTRL2);
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}
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static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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/* set EP mode */
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val = readl(priv->base + PCL_MODE);
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val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
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writel(val, priv->base + PCL_MODE);
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/* clock request */
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val = readl(priv->base + PCL_APP_CLK_CTRL);
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val &= ~PCL_APP_CLK_REQ;
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writel(val, priv->base + PCL_APP_CLK_CTRL);
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/* deassert PIPE3 and AXI reset */
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val = readl(priv->base + PCL_RSTCTRL0);
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val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
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| PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3;
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writel(val, priv->base + PCL_RSTCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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msleep(100);
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}
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static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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/* set EP mode */
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val = readl(priv->base + PCL_MODE);
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val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
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writel(val, priv->base + PCL_MODE);
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/* use auxiliary power detection */
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val = readl(priv->base + PCL_APP_PM0);
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val |= PCL_SYS_AUX_PWR_DET;
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writel(val, priv->base + PCL_APP_PM0);
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/* assert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
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| PCL_PERST_PLDN_REGVAL);
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val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
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| PCL_PERST_PLDN_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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usleep_range(100000, 200000);
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/* deassert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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}
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static int uniphier_pcie_nx1_wait_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 status;
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int ret;
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/* wait PIPE clock */
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ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
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status & PCL_PCLK_ALIVE, 100000, 1000000);
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if (ret) {
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dev_err(priv->pci.dev,
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"Failed to initialize controller in EP mode\n");
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return ret;
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}
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return 0;
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}
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static int uniphier_pcie_start_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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uniphier_pcie_ltssm_enable(priv, true);
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return 0;
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}
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static void uniphier_pcie_stop_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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uniphier_pcie_ltssm_enable(priv, false);
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}
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static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum pci_barno bar;
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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}
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static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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/*
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* This makes pulse signal to send INTx to the RC, so this should
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* be cleared as soon as possible. This sequence is covered with
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* mutex in pci_epc_raise_irq().
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*/
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/* assert INTx */
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val = readl(priv->base + PCL_APP_INTX);
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val |= PCL_APP_INTX_SYS_INT;
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writel(val, priv->base + PCL_APP_INTX);
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udelay(PCL_INTX_WIDTH_USEC);
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/* deassert INTx */
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val &= ~PCL_APP_INTX_SYS_INT;
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writel(val, priv->base + PCL_APP_INTX);
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return 0;
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}
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static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
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u8 func_no, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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u32 val;
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val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no)
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| FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1);
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writel(val, priv->base + PCL_APP_MSI0);
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val = readl(priv->base + PCL_APP_MSI1);
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val |= PCL_APP_MSI_REQ;
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writel(val, priv->base + PCL_APP_MSI1);
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return 0;
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}
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static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type,
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u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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return uniphier_pcie_ep_raise_legacy_irq(ep);
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case PCI_EPC_IRQ_MSI:
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return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
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interrupt_num);
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type);
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}
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return 0;
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}
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static const struct pci_epc_features*
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uniphier_pcie_get_features(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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return &priv->data->features;
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}
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static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
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.ep_init = uniphier_pcie_ep_init,
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.raise_irq = uniphier_pcie_ep_raise_irq,
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.get_features = uniphier_pcie_get_features,
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};
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static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
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{
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int ret;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clk_gio);
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if (ret)
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goto out_clk_disable;
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ret = reset_control_deassert(priv->rst);
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if (ret)
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goto out_clk_gio_disable;
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ret = reset_control_deassert(priv->rst_gio);
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if (ret)
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goto out_rst_assert;
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if (priv->data->init)
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priv->data->init(priv);
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uniphier_pcie_phy_reset(priv, true);
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ret = phy_init(priv->phy);
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if (ret)
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goto out_rst_gio_assert;
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uniphier_pcie_phy_reset(priv, false);
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if (priv->data->wait) {
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ret = priv->data->wait(priv);
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if (ret)
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goto out_phy_exit;
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}
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return 0;
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out_phy_exit:
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phy_exit(priv->phy);
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out_rst_gio_assert:
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reset_control_assert(priv->rst_gio);
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out_rst_assert:
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reset_control_assert(priv->rst);
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out_clk_gio_disable:
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clk_disable_unprepare(priv->clk_gio);
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out_clk_disable:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.start_link = uniphier_pcie_start_link,
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.stop_link = uniphier_pcie_stop_link,
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};
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static int uniphier_pcie_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_pcie_ep_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->data = of_device_get_match_data(dev);
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||
|
|
if (WARN_ON(!priv->data))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
priv->pci.dev = dev;
|
||
|
|
priv->pci.ops = &dw_pcie_ops;
|
||
|
|
|
||
|
|
priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
|
||
|
|
if (IS_ERR(priv->base))
|
||
|
|
return PTR_ERR(priv->base);
|
||
|
|
|
||
|
|
if (priv->data->has_gio) {
|
||
|
|
priv->clk_gio = devm_clk_get(dev, "gio");
|
||
|
|
if (IS_ERR(priv->clk_gio))
|
||
|
|
return PTR_ERR(priv->clk_gio);
|
||
|
|
|
||
|
|
priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
|
||
|
|
if (IS_ERR(priv->rst_gio))
|
||
|
|
return PTR_ERR(priv->rst_gio);
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->clk = devm_clk_get(dev, "link");
|
||
|
|
if (IS_ERR(priv->clk))
|
||
|
|
return PTR_ERR(priv->clk);
|
||
|
|
|
||
|
|
priv->rst = devm_reset_control_get_shared(dev, "link");
|
||
|
|
if (IS_ERR(priv->rst))
|
||
|
|
return PTR_ERR(priv->rst);
|
||
|
|
|
||
|
|
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
|
||
|
|
if (IS_ERR(priv->phy)) {
|
||
|
|
ret = PTR_ERR(priv->phy);
|
||
|
|
dev_err(dev, "Failed to get phy (%d)\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, priv);
|
||
|
|
|
||
|
|
ret = uniphier_pcie_ep_enable(priv);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
priv->pci.ep.ops = &uniphier_pcie_ep_ops;
|
||
|
|
return dw_pcie_ep_init(&priv->pci.ep);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
|
||
|
|
.has_gio = true,
|
||
|
|
.init = uniphier_pcie_pro5_init_ep,
|
||
|
|
.wait = NULL,
|
||
|
|
.features = {
|
||
|
|
.linkup_notifier = false,
|
||
|
|
.msi_capable = true,
|
||
|
|
.msix_capable = false,
|
||
|
|
.align = 1 << 16,
|
||
|
|
.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
|
||
|
|
.reserved_bar = BIT(BAR_4),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
|
||
|
|
.has_gio = false,
|
||
|
|
.init = uniphier_pcie_nx1_init_ep,
|
||
|
|
.wait = uniphier_pcie_nx1_wait_ep,
|
||
|
|
.features = {
|
||
|
|
.linkup_notifier = false,
|
||
|
|
.msi_capable = true,
|
||
|
|
.msix_capable = false,
|
||
|
|
.align = 1 << 12,
|
||
|
|
.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id uniphier_pcie_ep_match[] = {
|
||
|
|
{
|
||
|
|
.compatible = "socionext,uniphier-pro5-pcie-ep",
|
||
|
|
.data = &uniphier_pro5_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "socionext,uniphier-nx1-pcie-ep",
|
||
|
|
.data = &uniphier_nx1_data,
|
||
|
|
},
|
||
|
|
{ /* sentinel */ },
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver uniphier_pcie_ep_driver = {
|
||
|
|
.probe = uniphier_pcie_ep_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "uniphier-pcie-ep",
|
||
|
|
.of_match_table = uniphier_pcie_ep_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
builtin_platform_driver(uniphier_pcie_ep_driver);
|