540 lines
16 KiB
C
540 lines
16 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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/* DWC PCIe IP-core versions (native support since v4.70a) */
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#define DW_PCIE_VER_365A 0x3336352a
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#define DW_PCIE_VER_460A 0x3436302a
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#define DW_PCIE_VER_470A 0x3437302a
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#define DW_PCIE_VER_480A 0x3438302a
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#define DW_PCIE_VER_490A 0x3439302a
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#define DW_PCIE_VER_520A 0x3532302a
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#define __dw_pcie_ver_cmp(_pci, _ver, _op) \
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((_pci)->version _op DW_PCIE_VER_ ## _ver)
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#define dw_pcie_ver_is(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, ==)
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#define dw_pcie_ver_is_ge(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, >=)
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#define dw_pcie_ver_type_is(_pci, _ver, _type) \
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(__dw_pcie_ver_cmp(_pci, _ver, ==) && \
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__dw_pcie_ver_cmp(_pci, TYPE_ ## _type, ==))
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#define dw_pcie_ver_type_is_ge(_pci, _ver, _type) \
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(__dw_pcie_ver_cmp(_pci, _ver, ==) && \
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__dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=))
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU 9
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_AFR 0x70C
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#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
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#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
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#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
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#define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)
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#define PORT_AFR_ENTER_ASPM BIT(30)
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#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
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#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
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#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
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#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_DLL_LINK_EN BIT(5)
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#define PORT_LINK_FAST_LINK_MODE BIT(7)
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#define PORT_LINK_MODE_MASK GENMASK(21, 16)
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#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
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#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
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#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
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#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
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#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
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#define PCIE_PORT_DEBUG0 0x728
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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#define PCIE_PORT_DEBUG1 0x72C
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#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
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#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
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#define PORT_LOGIC_SPEED_CHANGE BIT(17)
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#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
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#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define GEN3_RELATED_OFF 0x890
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#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
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#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
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#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
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#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
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#define PCIE_VERSION_NUMBER 0x8F8
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#define PCIE_VERSION_TYPE 0x8FC
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/*
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* iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
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* iATU region CSRs had been indirectly accessible by means of the dedicated
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* viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
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* v4.80a in a way so the viewport was unrolled into the directly accessible
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* iATU/eDMA CSRs space.
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*/
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_DIR_IB BIT(31)
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#define PCIE_ATU_REGION_DIR_OB 0
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#define PCIE_ATU_VIEWPORT_BASE 0x904
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#define PCIE_ATU_UNROLL_BASE(dir, index) \
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(((index) << 9) | ((dir == PCIE_ATU_REGION_DIR_IB) ? BIT(8) : 0))
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#define PCIE_ATU_VIEWPORT_SIZE 0x2C
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#define PCIE_ATU_REGION_CTRL1 0x000
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#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13)
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#define PCIE_ATU_TYPE_MEM 0x0
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#define PCIE_ATU_TYPE_IO 0x2
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#define PCIE_ATU_TYPE_CFG0 0x4
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#define PCIE_ATU_TYPE_CFG1 0x5
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#define PCIE_ATU_TD BIT(8)
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#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
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#define PCIE_ATU_REGION_CTRL2 0x004
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#define PCIE_ATU_ENABLE BIT(31)
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#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
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#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
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#define PCIE_ATU_LOWER_BASE 0x008
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#define PCIE_ATU_UPPER_BASE 0x00C
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#define PCIE_ATU_LIMIT 0x010
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#define PCIE_ATU_LOWER_TARGET 0x014
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#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
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#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
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#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
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#define PCIE_ATU_UPPER_TARGET 0x018
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#define PCIE_ATU_UPPER_LIMIT 0x020
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#define PCIE_MISC_CONTROL_1_OFF 0x8BC
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#define PCIE_DBI_RO_WR_EN BIT(0)
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#define PCIE_MSIX_DOORBELL 0x948
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#define PCIE_MSIX_DOORBELL_PF_SHIFT 24
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#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
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#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
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#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
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#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)
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#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17)
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#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)
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#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0C
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#define PCIE_ATU_UNR_LOWER_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
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/*
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* RAS-DES register definitions
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*/
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#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8
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#define EVENT_COUNTER_ALL_CLEAR 0x3
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#define EVENT_COUNTER_ENABLE_ALL 0x7
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#define EVENT_COUNTER_ENABLE_SHIFT 2
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#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
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#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
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#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
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#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
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#define EVENT_COUNTER_EVENT_L1 0x5
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#define EVENT_COUNTER_EVENT_L1_1 0x7
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#define EVENT_COUNTER_EVENT_L1_2 0x8
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#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
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#define EVENT_COUNTER_GROUP_5 0x5
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#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc
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/*
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* The default address offset between dbi_base and atu_base. Root controller
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* drivers are not required to initialize atu_base if the offset matches this
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* default; the driver core automatically derives atu_base from dbi_base using
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* this offset, if atu_base not set.
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*/
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#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
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#define MAX_MSI_IRQS 256
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#define MAX_MSI_IRQS_PER_CTRL 32
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#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
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#define MSI_REG_CTRL_BLOCK_SIZE 12
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#define MSI_DEF_NUM_VECTORS 32
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/* Maximum number of inbound/outbound iATUs */
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#define MAX_IATU_IN 256
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#define MAX_IATU_OUT 256
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struct dw_pcie;
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struct dw_pcie_rp;
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struct dw_pcie_ep;
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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struct dw_pcie_host_ops {
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int (*host_init)(struct dw_pcie_rp *pp);
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void (*host_deinit)(struct dw_pcie_rp *pp);
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int (*msi_host_init)(struct dw_pcie_rp *pp);
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};
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struct dw_pcie_rp {
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bool has_msi_ctrl:1;
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bool cfg0_io_shared:1;
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u64 cfg0_base;
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void __iomem *va_cfg0_base;
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u32 cfg0_size;
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resource_size_t io_base;
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phys_addr_t io_bus_addr;
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u32 io_size;
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int irq;
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const struct dw_pcie_host_ops *ops;
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int msi_irq[MAX_MSI_CTRLS];
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struct irq_domain *irq_domain;
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struct irq_domain *msi_domain;
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dma_addr_t msi_data;
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struct irq_chip *msi_irq_chip;
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u32 num_vectors;
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u32 irq_mask[MAX_MSI_CTRLS];
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struct pci_host_bridge *bridge;
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raw_spinlock_t lock;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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};
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struct dw_pcie_ep_ops {
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void (*ep_init)(struct dw_pcie_ep *ep);
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int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u16 interrupt_num);
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const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
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/*
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* Provide a method to implement the different func config space
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* access for different platform, if different func have different
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* offset, return the offset of func. if use write a register way
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* return a 0, and implement code in callback function of platform
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* driver.
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*/
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unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
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};
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struct dw_pcie_ep_func {
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struct list_head list;
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u8 func_no;
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u8 msi_cap; /* MSI capability offset */
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u8 msix_cap; /* MSI-X capability offset */
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};
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struct dw_pcie_ep {
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struct pci_epc *epc;
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struct list_head func_list;
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const struct dw_pcie_ep_ops *ops;
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phys_addr_t phys_base;
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size_t addr_size;
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size_t page_size;
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u8 bar_to_atu[PCI_STD_NUM_BARS];
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phys_addr_t *outbound_addr;
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unsigned long *ib_window_map;
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unsigned long *ob_window_map;
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void __iomem *msi_mem;
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phys_addr_t msi_mem_phys;
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struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
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};
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struct dw_pcie_ops {
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u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
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u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size);
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void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size, u32 val);
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void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size, u32 val);
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int (*link_up)(struct dw_pcie *pcie);
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int (*start_link)(struct dw_pcie *pcie);
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void (*stop_link)(struct dw_pcie *pcie);
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};
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struct dw_pcie {
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struct device *dev;
|
||
|
|
void __iomem *dbi_base;
|
||
|
|
void __iomem *dbi_base2;
|
||
|
|
void __iomem *atu_base;
|
||
|
|
size_t atu_size;
|
||
|
|
u32 num_ib_windows;
|
||
|
|
u32 num_ob_windows;
|
||
|
|
u32 region_align;
|
||
|
|
u64 region_limit;
|
||
|
|
struct dw_pcie_rp pp;
|
||
|
|
struct dw_pcie_ep ep;
|
||
|
|
const struct dw_pcie_ops *ops;
|
||
|
|
u32 version;
|
||
|
|
u32 type;
|
||
|
|
int num_lanes;
|
||
|
|
int link_gen;
|
||
|
|
u8 n_fts[2];
|
||
|
|
bool iatu_unroll_enabled: 1;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
|
||
|
|
|
||
|
|
#define to_dw_pcie_from_ep(endpoint) \
|
||
|
|
container_of((endpoint), struct dw_pcie, ep)
|
||
|
|
|
||
|
|
void dw_pcie_version_detect(struct dw_pcie *pci);
|
||
|
|
|
||
|
|
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
|
||
|
|
u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
|
||
|
|
|
||
|
|
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
|
||
|
|
int dw_pcie_write(void __iomem *addr, int size, u32 val);
|
||
|
|
|
||
|
|
u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);
|
||
|
|
void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
|
||
|
|
void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
|
||
|
|
int dw_pcie_link_up(struct dw_pcie *pci);
|
||
|
|
void dw_pcie_upconfig_setup(struct dw_pcie *pci);
|
||
|
|
int dw_pcie_wait_for_link(struct dw_pcie *pci);
|
||
|
|
int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
|
||
|
|
u64 cpu_addr, u64 pci_addr, u64 size);
|
||
|
|
int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
|
||
|
|
int type, u64 cpu_addr, u64 pci_addr, u64 size);
|
||
|
|
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
|
||
|
|
int type, u64 cpu_addr, u8 bar);
|
||
|
|
void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);
|
||
|
|
void dw_pcie_setup(struct dw_pcie *pci);
|
||
|
|
void dw_pcie_iatu_detect(struct dw_pcie *pci);
|
||
|
|
|
||
|
|
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
|
||
|
|
{
|
||
|
|
dw_pcie_write_dbi(pci, reg, 0x4, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
|
||
|
|
{
|
||
|
|
return dw_pcie_read_dbi(pci, reg, 0x4);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
|
||
|
|
{
|
||
|
|
dw_pcie_write_dbi(pci, reg, 0x2, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
|
||
|
|
{
|
||
|
|
return dw_pcie_read_dbi(pci, reg, 0x2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
|
||
|
|
{
|
||
|
|
dw_pcie_write_dbi(pci, reg, 0x1, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
|
||
|
|
{
|
||
|
|
return dw_pcie_read_dbi(pci, reg, 0x1);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
|
||
|
|
{
|
||
|
|
dw_pcie_write_dbi2(pci, reg, 0x4, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
|
||
|
|
{
|
||
|
|
u32 reg;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
reg = PCIE_MISC_CONTROL_1_OFF;
|
||
|
|
val = dw_pcie_readl_dbi(pci, reg);
|
||
|
|
val |= PCIE_DBI_RO_WR_EN;
|
||
|
|
dw_pcie_writel_dbi(pci, reg, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
|
||
|
|
{
|
||
|
|
u32 reg;
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
reg = PCIE_MISC_CONTROL_1_OFF;
|
||
|
|
val = dw_pcie_readl_dbi(pci, reg);
|
||
|
|
val &= ~PCIE_DBI_RO_WR_EN;
|
||
|
|
dw_pcie_writel_dbi(pci, reg, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_start_link(struct dw_pcie *pci)
|
||
|
|
{
|
||
|
|
if (pci->ops && pci->ops->start_link)
|
||
|
|
return pci->ops->start_link(pci);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_stop_link(struct dw_pcie *pci)
|
||
|
|
{
|
||
|
|
if (pci->ops && pci->ops->stop_link)
|
||
|
|
pci->ops->stop_link(pci);
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PCIE_DW_HOST
|
||
|
|
irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
|
||
|
|
int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
|
||
|
|
int dw_pcie_host_init(struct dw_pcie_rp *pp);
|
||
|
|
void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
|
||
|
|
int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);
|
||
|
|
void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
|
||
|
|
int where);
|
||
|
|
#else
|
||
|
|
static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
|
||
|
|
{
|
||
|
|
return IRQ_NONE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_host_init(struct dw_pcie_rp *pp)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
|
||
|
|
unsigned int devfn,
|
||
|
|
int where)
|
||
|
|
{
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_PCIE_DW_EP
|
||
|
|
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
|
||
|
|
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
|
||
|
|
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
|
||
|
|
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
|
||
|
|
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
|
||
|
|
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
|
||
|
|
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
u8 interrupt_num);
|
||
|
|
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
u16 interrupt_num);
|
||
|
|
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
u16 interrupt_num);
|
||
|
|
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
|
||
|
|
struct dw_pcie_ep_func *
|
||
|
|
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no);
|
||
|
|
#else
|
||
|
|
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
u8 interrupt_num)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
u16 interrupt_num)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
|
||
|
|
u8 func_no,
|
||
|
|
u16 interrupt_num)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline struct dw_pcie_ep_func *
|
||
|
|
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
|
||
|
|
{
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#endif /* _PCIE_DESIGNWARE_H */
|