315 lines
8.0 KiB
C
315 lines
8.0 KiB
C
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// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc. */
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#include "mt7921.h"
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#include "../dma.h"
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#include "mac.h"
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static int mt7921_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt7921_dev *dev;
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dev = container_of(napi, struct mt7921_dev, mt76.tx_napi);
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if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
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napi_complete(napi);
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queue_work(dev->mt76.wq, &dev->pm.wake_work);
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return 0;
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}
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mt76_connac_tx_cleanup(&dev->mt76);
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if (napi_complete(napi))
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mt7921_irq_enable(dev, MT_INT_TX_DONE_ALL);
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mt76_connac_pm_unref(&dev->mphy, &dev->pm);
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return 0;
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}
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static int mt7921_poll_rx(struct napi_struct *napi, int budget)
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{
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struct mt7921_dev *dev;
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int done;
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dev = container_of(napi->dev, struct mt7921_dev, mt76.napi_dev);
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if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
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napi_complete(napi);
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queue_work(dev->mt76.wq, &dev->pm.wake_work);
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return 0;
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}
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done = mt76_dma_rx_poll(napi, budget);
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mt76_connac_pm_unref(&dev->mphy, &dev->pm);
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return done;
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}
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static void mt7921_dma_prefetch(struct mt7921_dev *dev)
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{
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#define PREFETCH(base, depth) ((base) << 16 | (depth))
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mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
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mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
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mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
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}
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static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)
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{
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/* disable WFDMA0 */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (!mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
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MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1))
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return -ETIMEDOUT;
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/* disable dmashdl */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0,
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MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);
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mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);
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if (force) {
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/* reset */
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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}
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return 0;
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}
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static int mt7921_dma_enable(struct mt7921_dev *dev)
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{
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/* configure perfetch settings */
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mt7921_dma_prefetch(dev);
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/* reset dma idx */
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
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/* configure delay interrupt */
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
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MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
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MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
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mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);
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/* enable interrupts for TX/RX rings */
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mt7921_irq_enable(dev,
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MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_MCU_CMD);
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mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
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return 0;
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}
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static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)
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{
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int i, err;
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err = mt7921_dma_disable(dev, force);
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if (err)
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return err;
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/* reset hw queues */
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_reset(dev, dev->mphy.q_tx[i]);
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for (i = 0; i < __MT_MCUQ_MAX; i++)
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mt76_queue_reset(dev, dev->mt76.q_mcu[i]);
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mt76_for_each_q_rx(&dev->mt76, i)
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mt76_queue_reset(dev, &dev->mt76.q_rx[i]);
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mt76_tx_status_check(&dev->mt76, true);
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return mt7921_dma_enable(dev);
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}
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int mt7921_wfsys_reset(struct mt7921_dev *dev)
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{
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mt76_clear(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
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msleep(50);
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mt76_set(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
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if (!__mt76_poll_msec(&dev->mt76, MT_WFSYS_SW_RST_B,
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WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500))
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return -ETIMEDOUT;
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return 0;
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}
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int mt7921_wpdma_reset(struct mt7921_dev *dev, bool force)
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{
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int i, err;
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/* clean up hw queues */
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for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
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mt76_for_each_q_rx(&dev->mt76, i)
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mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);
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if (force) {
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err = mt7921_wfsys_reset(dev);
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if (err)
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return err;
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}
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err = mt7921_dma_reset(dev, force);
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if (err)
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return err;
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mt76_for_each_q_rx(&dev->mt76, i)
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mt76_queue_rx_reset(dev, i);
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return 0;
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}
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int mt7921_wpdma_reinit_cond(struct mt7921_dev *dev)
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{
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struct mt76_connac_pm *pm = &dev->pm;
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int err;
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/* check if the wpdma must be reinitialized */
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if (mt7921_dma_need_reinit(dev)) {
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/* disable interrutpts */
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
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err = mt7921_wpdma_reset(dev, false);
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if (err) {
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dev_err(dev->mt76.dev, "wpdma reset failed\n");
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return err;
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}
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/* enable interrutpts */
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mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
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pm->stats.lp_wake++;
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}
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return 0;
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}
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int mt7921_dma_init(struct mt7921_dev *dev)
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{
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int ret;
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mt76_dma_attach(&dev->mt76);
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ret = mt7921_dma_disable(dev, true);
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if (ret)
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return ret;
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/* init tx queue */
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ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
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MT7921_TX_RING_SIZE,
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MT_TX_RING_BASE, 0);
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if (ret)
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return ret;
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mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
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/* command to WM */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
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MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
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if (ret)
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return ret;
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/* firmware download */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
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MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
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if (ret)
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return ret;
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/* event from WM before firmware download */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
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MT7921_RXQ_MCU_WM,
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MT7921_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
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if (ret)
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return ret;
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/* Change mcu queue after firmware download */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
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MT7921_RXQ_MCU_WM,
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MT7921_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
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if (ret)
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return ret;
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/* rx data */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
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MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
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MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
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if (ret)
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return ret;
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ret = mt76_init_queues(dev, mt7921_poll_rx);
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if (ret < 0)
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return ret;
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netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
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mt7921_poll_tx);
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napi_enable(&dev->mt76.tx_napi);
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return mt7921_dma_enable(dev);
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}
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void mt7921_dma_cleanup(struct mt7921_dev *dev)
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{
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/* disable */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
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MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1);
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/* reset */
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_dma_cleanup(&dev->mt76);
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}
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