596 lines
18 KiB
ArmAsm
596 lines
18 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* SM4 Cipher Algorithm, AES-NI/AVX optimized.
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* as specified in
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* https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
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*
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* Copyright (C) 2018 Markku-Juhani O. Saarinen <mjos@iki.fi>
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* Copyright (C) 2020 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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* Copyright (c) 2021 Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
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*/
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/* Based on SM4 AES-NI work by libgcrypt and Markku-Juhani O. Saarinen at:
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* https://github.com/mjosaarinen/sm4ni
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*/
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#include <linux/linkage.h>
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#include <linux/cfi_types.h>
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#include <asm/frame.h>
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#define rRIP (%rip)
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#define RX0 %xmm0
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#define RX1 %xmm1
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#define MASK_4BIT %xmm2
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#define RTMP0 %xmm3
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#define RTMP1 %xmm4
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#define RTMP2 %xmm5
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#define RTMP3 %xmm6
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#define RTMP4 %xmm7
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#define RA0 %xmm8
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#define RA1 %xmm9
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#define RA2 %xmm10
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#define RA3 %xmm11
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#define RB0 %xmm12
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#define RB1 %xmm13
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#define RB2 %xmm14
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#define RB3 %xmm15
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#define RNOT %xmm0
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#define RBSWAP %xmm1
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/* Transpose four 32-bit words between 128-bit vectors. */
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#define transpose_4x4(x0, x1, x2, x3, t1, t2) \
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vpunpckhdq x1, x0, t2; \
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vpunpckldq x1, x0, x0; \
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\
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vpunpckldq x3, x2, t1; \
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vpunpckhdq x3, x2, x2; \
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\
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vpunpckhqdq t1, x0, x1; \
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vpunpcklqdq t1, x0, x0; \
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\
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vpunpckhqdq x2, t2, x3; \
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vpunpcklqdq x2, t2, x2;
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/* pre-SubByte transform. */
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#define transform_pre(x, lo_t, hi_t, mask4bit, tmp0) \
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vpand x, mask4bit, tmp0; \
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vpandn x, mask4bit, x; \
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vpsrld $4, x, x; \
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\
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vpshufb tmp0, lo_t, tmp0; \
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vpshufb x, hi_t, x; \
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vpxor tmp0, x, x;
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/* post-SubByte transform. Note: x has been XOR'ed with mask4bit by
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* 'vaeslastenc' instruction.
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*/
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#define transform_post(x, lo_t, hi_t, mask4bit, tmp0) \
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vpandn mask4bit, x, tmp0; \
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vpsrld $4, x, x; \
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vpand x, mask4bit, x; \
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\
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vpshufb tmp0, lo_t, tmp0; \
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vpshufb x, hi_t, x; \
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vpxor tmp0, x, x;
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.section .rodata.cst16, "aM", @progbits, 16
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.align 16
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/*
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* Following four affine transform look-up tables are from work by
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* Markku-Juhani O. Saarinen, at https://github.com/mjosaarinen/sm4ni
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*
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* These allow exposing SM4 S-Box from AES SubByte.
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*/
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/* pre-SubByte affine transform, from SM4 field to AES field. */
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.Lpre_tf_lo_s:
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.quad 0x9197E2E474720701, 0xC7C1B4B222245157
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.Lpre_tf_hi_s:
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.quad 0xE240AB09EB49A200, 0xF052B91BF95BB012
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/* post-SubByte affine transform, from AES field to SM4 field. */
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.Lpost_tf_lo_s:
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.quad 0x5B67F2CEA19D0834, 0xEDD14478172BBE82
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.Lpost_tf_hi_s:
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.quad 0xAE7201DD73AFDC00, 0x11CDBE62CC1063BF
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/* For isolating SubBytes from AESENCLAST, inverse shift row */
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.Linv_shift_row:
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.byte 0x00, 0x0d, 0x0a, 0x07, 0x04, 0x01, 0x0e, 0x0b
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.byte 0x08, 0x05, 0x02, 0x0f, 0x0c, 0x09, 0x06, 0x03
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/* Inverse shift row + Rotate left by 8 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_8:
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.byte 0x07, 0x00, 0x0d, 0x0a, 0x0b, 0x04, 0x01, 0x0e
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.byte 0x0f, 0x08, 0x05, 0x02, 0x03, 0x0c, 0x09, 0x06
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/* Inverse shift row + Rotate left by 16 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_16:
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.byte 0x0a, 0x07, 0x00, 0x0d, 0x0e, 0x0b, 0x04, 0x01
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.byte 0x02, 0x0f, 0x08, 0x05, 0x06, 0x03, 0x0c, 0x09
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/* Inverse shift row + Rotate left by 24 bits on 32-bit words with vpshufb */
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.Linv_shift_row_rol_24:
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.byte 0x0d, 0x0a, 0x07, 0x00, 0x01, 0x0e, 0x0b, 0x04
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.byte 0x05, 0x02, 0x0f, 0x08, 0x09, 0x06, 0x03, 0x0c
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/* For CTR-mode IV byteswap */
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.Lbswap128_mask:
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.byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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/* For input word byte-swap */
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.Lbswap32_mask:
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.byte 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
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.align 4
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/* 4-bit mask */
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.L0f0f0f0f:
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.long 0x0f0f0f0f
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/* 12 bytes, only for padding */
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.Lpadding_deadbeef:
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.long 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
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.text
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.align 16
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/*
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* void sm4_aesni_avx_crypt4(const u32 *rk, u8 *dst,
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* const u8 *src, int nblocks)
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*/
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.align 8
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SYM_FUNC_START(sm4_aesni_avx_crypt4)
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/* input:
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* %rdi: round key array, CTX
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* %rsi: dst (1..4 blocks)
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* %rdx: src (1..4 blocks)
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* %rcx: num blocks (1..4)
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*/
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FRAME_BEGIN
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vmovdqu 0*16(%rdx), RA0;
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vmovdqa RA0, RA1;
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vmovdqa RA0, RA2;
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vmovdqa RA0, RA3;
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cmpq $2, %rcx;
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jb .Lblk4_load_input_done;
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vmovdqu 1*16(%rdx), RA1;
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je .Lblk4_load_input_done;
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vmovdqu 2*16(%rdx), RA2;
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cmpq $3, %rcx;
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je .Lblk4_load_input_done;
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vmovdqu 3*16(%rdx), RA3;
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.Lblk4_load_input_done:
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vmovdqa .Lbswap32_mask rRIP, RTMP2;
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vpshufb RTMP2, RA0, RA0;
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vpshufb RTMP2, RA1, RA1;
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vpshufb RTMP2, RA2, RA2;
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vpshufb RTMP2, RA3, RA3;
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vbroadcastss .L0f0f0f0f rRIP, MASK_4BIT;
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vmovdqa .Lpre_tf_lo_s rRIP, RTMP4;
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vmovdqa .Lpre_tf_hi_s rRIP, RB0;
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vmovdqa .Lpost_tf_lo_s rRIP, RB1;
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vmovdqa .Lpost_tf_hi_s rRIP, RB2;
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vmovdqa .Linv_shift_row rRIP, RB3;
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vmovdqa .Linv_shift_row_rol_8 rRIP, RTMP2;
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vmovdqa .Linv_shift_row_rol_16 rRIP, RTMP3;
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transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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#define ROUND(round, s0, s1, s2, s3) \
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vbroadcastss (4*(round))(%rdi), RX0; \
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vpxor s1, RX0, RX0; \
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vpxor s2, RX0, RX0; \
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vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */ \
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\
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/* sbox, non-linear part */ \
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transform_pre(RX0, RTMP4, RB0, MASK_4BIT, RTMP0); \
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vaesenclast MASK_4BIT, RX0, RX0; \
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transform_post(RX0, RB1, RB2, MASK_4BIT, RTMP0); \
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\
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/* linear part */ \
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vpshufb RB3, RX0, RTMP0; \
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vpxor RTMP0, s0, s0; /* s0 ^ x */ \
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vpshufb RTMP2, RX0, RTMP1; \
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vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) */ \
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vpshufb RTMP3, RX0, RTMP1; \
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vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) ^ rol(x,16) */ \
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vpshufb .Linv_shift_row_rol_24 rRIP, RX0, RTMP1; \
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vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */ \
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vpslld $2, RTMP0, RTMP1; \
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vpsrld $30, RTMP0, RTMP0; \
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vpxor RTMP0, s0, s0; \
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/* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
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vpxor RTMP1, s0, s0;
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leaq (32*4)(%rdi), %rax;
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.align 16
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.Lroundloop_blk4:
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ROUND(0, RA0, RA1, RA2, RA3);
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ROUND(1, RA1, RA2, RA3, RA0);
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ROUND(2, RA2, RA3, RA0, RA1);
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ROUND(3, RA3, RA0, RA1, RA2);
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leaq (4*4)(%rdi), %rdi;
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cmpq %rax, %rdi;
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jne .Lroundloop_blk4;
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#undef ROUND
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vmovdqa .Lbswap128_mask rRIP, RTMP2;
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transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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vpshufb RTMP2, RA0, RA0;
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vpshufb RTMP2, RA1, RA1;
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vpshufb RTMP2, RA2, RA2;
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vpshufb RTMP2, RA3, RA3;
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vmovdqu RA0, 0*16(%rsi);
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cmpq $2, %rcx;
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jb .Lblk4_store_output_done;
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vmovdqu RA1, 1*16(%rsi);
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je .Lblk4_store_output_done;
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vmovdqu RA2, 2*16(%rsi);
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cmpq $3, %rcx;
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je .Lblk4_store_output_done;
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vmovdqu RA3, 3*16(%rsi);
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.Lblk4_store_output_done:
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vzeroall;
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FRAME_END
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RET;
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SYM_FUNC_END(sm4_aesni_avx_crypt4)
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.align 8
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SYM_FUNC_START_LOCAL(__sm4_crypt_blk8)
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/* input:
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* %rdi: round key array, CTX
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* RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3: eight parallel
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* plaintext blocks
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* output:
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* RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3: eight parallel
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* ciphertext blocks
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*/
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FRAME_BEGIN
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vmovdqa .Lbswap32_mask rRIP, RTMP2;
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vpshufb RTMP2, RA0, RA0;
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vpshufb RTMP2, RA1, RA1;
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vpshufb RTMP2, RA2, RA2;
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vpshufb RTMP2, RA3, RA3;
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vpshufb RTMP2, RB0, RB0;
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vpshufb RTMP2, RB1, RB1;
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vpshufb RTMP2, RB2, RB2;
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vpshufb RTMP2, RB3, RB3;
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vbroadcastss .L0f0f0f0f rRIP, MASK_4BIT;
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transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
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transpose_4x4(RB0, RB1, RB2, RB3, RTMP0, RTMP1);
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#define ROUND(round, s0, s1, s2, s3, r0, r1, r2, r3) \
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vbroadcastss (4*(round))(%rdi), RX0; \
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vmovdqa .Lpre_tf_lo_s rRIP, RTMP4; \
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vmovdqa .Lpre_tf_hi_s rRIP, RTMP1; \
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vmovdqa RX0, RX1; \
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vpxor s1, RX0, RX0; \
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vpxor s2, RX0, RX0; \
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vpxor s3, RX0, RX0; /* s1 ^ s2 ^ s3 ^ rk */ \
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vmovdqa .Lpost_tf_lo_s rRIP, RTMP2; \
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vmovdqa .Lpost_tf_hi_s rRIP, RTMP3; \
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vpxor r1, RX1, RX1; \
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vpxor r2, RX1, RX1; \
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vpxor r3, RX1, RX1; /* r1 ^ r2 ^ r3 ^ rk */ \
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\
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/* sbox, non-linear part */ \
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transform_pre(RX0, RTMP4, RTMP1, MASK_4BIT, RTMP0); \
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transform_pre(RX1, RTMP4, RTMP1, MASK_4BIT, RTMP0); \
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vmovdqa .Linv_shift_row rRIP, RTMP4; \
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vaesenclast MASK_4BIT, RX0, RX0; \
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vaesenclast MASK_4BIT, RX1, RX1; \
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transform_post(RX0, RTMP2, RTMP3, MASK_4BIT, RTMP0); \
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transform_post(RX1, RTMP2, RTMP3, MASK_4BIT, RTMP0); \
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\
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/* linear part */ \
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vpshufb RTMP4, RX0, RTMP0; \
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vpxor RTMP0, s0, s0; /* s0 ^ x */ \
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vpshufb RTMP4, RX1, RTMP2; \
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vmovdqa .Linv_shift_row_rol_8 rRIP, RTMP4; \
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vpxor RTMP2, r0, r0; /* r0 ^ x */ \
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vpshufb RTMP4, RX0, RTMP1; \
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vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) */ \
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vpshufb RTMP4, RX1, RTMP3; \
|
||
|
|
vmovdqa .Linv_shift_row_rol_16 rRIP, RTMP4; \
|
||
|
|
vpxor RTMP3, RTMP2, RTMP2; /* x ^ rol(x,8) */ \
|
||
|
|
vpshufb RTMP4, RX0, RTMP1; \
|
||
|
|
vpxor RTMP1, RTMP0, RTMP0; /* x ^ rol(x,8) ^ rol(x,16) */ \
|
||
|
|
vpshufb RTMP4, RX1, RTMP3; \
|
||
|
|
vmovdqa .Linv_shift_row_rol_24 rRIP, RTMP4; \
|
||
|
|
vpxor RTMP3, RTMP2, RTMP2; /* x ^ rol(x,8) ^ rol(x,16) */ \
|
||
|
|
vpshufb RTMP4, RX0, RTMP1; \
|
||
|
|
vpxor RTMP1, s0, s0; /* s0 ^ x ^ rol(x,24) */ \
|
||
|
|
/* s0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
|
||
|
|
vpslld $2, RTMP0, RTMP1; \
|
||
|
|
vpsrld $30, RTMP0, RTMP0; \
|
||
|
|
vpxor RTMP0, s0, s0; \
|
||
|
|
vpxor RTMP1, s0, s0; \
|
||
|
|
vpshufb RTMP4, RX1, RTMP3; \
|
||
|
|
vpxor RTMP3, r0, r0; /* r0 ^ x ^ rol(x,24) */ \
|
||
|
|
/* r0 ^ x ^ rol(x,2) ^ rol(x,10) ^ rol(x,18) ^ rol(x,24) */ \
|
||
|
|
vpslld $2, RTMP2, RTMP3; \
|
||
|
|
vpsrld $30, RTMP2, RTMP2; \
|
||
|
|
vpxor RTMP2, r0, r0; \
|
||
|
|
vpxor RTMP3, r0, r0;
|
||
|
|
|
||
|
|
leaq (32*4)(%rdi), %rax;
|
||
|
|
.align 16
|
||
|
|
.Lroundloop_blk8:
|
||
|
|
ROUND(0, RA0, RA1, RA2, RA3, RB0, RB1, RB2, RB3);
|
||
|
|
ROUND(1, RA1, RA2, RA3, RA0, RB1, RB2, RB3, RB0);
|
||
|
|
ROUND(2, RA2, RA3, RA0, RA1, RB2, RB3, RB0, RB1);
|
||
|
|
ROUND(3, RA3, RA0, RA1, RA2, RB3, RB0, RB1, RB2);
|
||
|
|
leaq (4*4)(%rdi), %rdi;
|
||
|
|
cmpq %rax, %rdi;
|
||
|
|
jne .Lroundloop_blk8;
|
||
|
|
|
||
|
|
#undef ROUND
|
||
|
|
|
||
|
|
vmovdqa .Lbswap128_mask rRIP, RTMP2;
|
||
|
|
|
||
|
|
transpose_4x4(RA0, RA1, RA2, RA3, RTMP0, RTMP1);
|
||
|
|
transpose_4x4(RB0, RB1, RB2, RB3, RTMP0, RTMP1);
|
||
|
|
vpshufb RTMP2, RA0, RA0;
|
||
|
|
vpshufb RTMP2, RA1, RA1;
|
||
|
|
vpshufb RTMP2, RA2, RA2;
|
||
|
|
vpshufb RTMP2, RA3, RA3;
|
||
|
|
vpshufb RTMP2, RB0, RB0;
|
||
|
|
vpshufb RTMP2, RB1, RB1;
|
||
|
|
vpshufb RTMP2, RB2, RB2;
|
||
|
|
vpshufb RTMP2, RB3, RB3;
|
||
|
|
|
||
|
|
FRAME_END
|
||
|
|
RET;
|
||
|
|
SYM_FUNC_END(__sm4_crypt_blk8)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void sm4_aesni_avx_crypt8(const u32 *rk, u8 *dst,
|
||
|
|
* const u8 *src, int nblocks)
|
||
|
|
*/
|
||
|
|
.align 8
|
||
|
|
SYM_FUNC_START(sm4_aesni_avx_crypt8)
|
||
|
|
/* input:
|
||
|
|
* %rdi: round key array, CTX
|
||
|
|
* %rsi: dst (1..8 blocks)
|
||
|
|
* %rdx: src (1..8 blocks)
|
||
|
|
* %rcx: num blocks (1..8)
|
||
|
|
*/
|
||
|
|
cmpq $5, %rcx;
|
||
|
|
jb sm4_aesni_avx_crypt4;
|
||
|
|
|
||
|
|
FRAME_BEGIN
|
||
|
|
|
||
|
|
vmovdqu (0 * 16)(%rdx), RA0;
|
||
|
|
vmovdqu (1 * 16)(%rdx), RA1;
|
||
|
|
vmovdqu (2 * 16)(%rdx), RA2;
|
||
|
|
vmovdqu (3 * 16)(%rdx), RA3;
|
||
|
|
vmovdqu (4 * 16)(%rdx), RB0;
|
||
|
|
vmovdqa RB0, RB1;
|
||
|
|
vmovdqa RB0, RB2;
|
||
|
|
vmovdqa RB0, RB3;
|
||
|
|
je .Lblk8_load_input_done;
|
||
|
|
vmovdqu (5 * 16)(%rdx), RB1;
|
||
|
|
cmpq $7, %rcx;
|
||
|
|
jb .Lblk8_load_input_done;
|
||
|
|
vmovdqu (6 * 16)(%rdx), RB2;
|
||
|
|
je .Lblk8_load_input_done;
|
||
|
|
vmovdqu (7 * 16)(%rdx), RB3;
|
||
|
|
|
||
|
|
.Lblk8_load_input_done:
|
||
|
|
call __sm4_crypt_blk8;
|
||
|
|
|
||
|
|
cmpq $6, %rcx;
|
||
|
|
vmovdqu RA0, (0 * 16)(%rsi);
|
||
|
|
vmovdqu RA1, (1 * 16)(%rsi);
|
||
|
|
vmovdqu RA2, (2 * 16)(%rsi);
|
||
|
|
vmovdqu RA3, (3 * 16)(%rsi);
|
||
|
|
vmovdqu RB0, (4 * 16)(%rsi);
|
||
|
|
jb .Lblk8_store_output_done;
|
||
|
|
vmovdqu RB1, (5 * 16)(%rsi);
|
||
|
|
je .Lblk8_store_output_done;
|
||
|
|
vmovdqu RB2, (6 * 16)(%rsi);
|
||
|
|
cmpq $7, %rcx;
|
||
|
|
je .Lblk8_store_output_done;
|
||
|
|
vmovdqu RB3, (7 * 16)(%rsi);
|
||
|
|
|
||
|
|
.Lblk8_store_output_done:
|
||
|
|
vzeroall;
|
||
|
|
FRAME_END
|
||
|
|
RET;
|
||
|
|
SYM_FUNC_END(sm4_aesni_avx_crypt8)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void sm4_aesni_avx_ctr_enc_blk8(const u32 *rk, u8 *dst,
|
||
|
|
* const u8 *src, u8 *iv)
|
||
|
|
*/
|
||
|
|
.align 8
|
||
|
|
SYM_TYPED_FUNC_START(sm4_aesni_avx_ctr_enc_blk8)
|
||
|
|
/* input:
|
||
|
|
* %rdi: round key array, CTX
|
||
|
|
* %rsi: dst (8 blocks)
|
||
|
|
* %rdx: src (8 blocks)
|
||
|
|
* %rcx: iv (big endian, 128bit)
|
||
|
|
*/
|
||
|
|
FRAME_BEGIN
|
||
|
|
|
||
|
|
/* load IV and byteswap */
|
||
|
|
vmovdqu (%rcx), RA0;
|
||
|
|
|
||
|
|
vmovdqa .Lbswap128_mask rRIP, RBSWAP;
|
||
|
|
vpshufb RBSWAP, RA0, RTMP0; /* be => le */
|
||
|
|
|
||
|
|
vpcmpeqd RNOT, RNOT, RNOT;
|
||
|
|
vpsrldq $8, RNOT, RNOT; /* low: -1, high: 0 */
|
||
|
|
|
||
|
|
#define inc_le128(x, minus_one, tmp) \
|
||
|
|
vpcmpeqq minus_one, x, tmp; \
|
||
|
|
vpsubq minus_one, x, x; \
|
||
|
|
vpslldq $8, tmp, tmp; \
|
||
|
|
vpsubq tmp, x, x;
|
||
|
|
|
||
|
|
/* construct IVs */
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +1 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RA1;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +2 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RA2;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +3 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RA3;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +4 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RB0;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +5 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RB1;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +6 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RB2;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +7 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RB3;
|
||
|
|
inc_le128(RTMP0, RNOT, RTMP2); /* +8 */
|
||
|
|
vpshufb RBSWAP, RTMP0, RTMP1;
|
||
|
|
|
||
|
|
/* store new IV */
|
||
|
|
vmovdqu RTMP1, (%rcx);
|
||
|
|
|
||
|
|
call __sm4_crypt_blk8;
|
||
|
|
|
||
|
|
vpxor (0 * 16)(%rdx), RA0, RA0;
|
||
|
|
vpxor (1 * 16)(%rdx), RA1, RA1;
|
||
|
|
vpxor (2 * 16)(%rdx), RA2, RA2;
|
||
|
|
vpxor (3 * 16)(%rdx), RA3, RA3;
|
||
|
|
vpxor (4 * 16)(%rdx), RB0, RB0;
|
||
|
|
vpxor (5 * 16)(%rdx), RB1, RB1;
|
||
|
|
vpxor (6 * 16)(%rdx), RB2, RB2;
|
||
|
|
vpxor (7 * 16)(%rdx), RB3, RB3;
|
||
|
|
|
||
|
|
vmovdqu RA0, (0 * 16)(%rsi);
|
||
|
|
vmovdqu RA1, (1 * 16)(%rsi);
|
||
|
|
vmovdqu RA2, (2 * 16)(%rsi);
|
||
|
|
vmovdqu RA3, (3 * 16)(%rsi);
|
||
|
|
vmovdqu RB0, (4 * 16)(%rsi);
|
||
|
|
vmovdqu RB1, (5 * 16)(%rsi);
|
||
|
|
vmovdqu RB2, (6 * 16)(%rsi);
|
||
|
|
vmovdqu RB3, (7 * 16)(%rsi);
|
||
|
|
|
||
|
|
vzeroall;
|
||
|
|
FRAME_END
|
||
|
|
RET;
|
||
|
|
SYM_FUNC_END(sm4_aesni_avx_ctr_enc_blk8)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void sm4_aesni_avx_cbc_dec_blk8(const u32 *rk, u8 *dst,
|
||
|
|
* const u8 *src, u8 *iv)
|
||
|
|
*/
|
||
|
|
.align 8
|
||
|
|
SYM_TYPED_FUNC_START(sm4_aesni_avx_cbc_dec_blk8)
|
||
|
|
/* input:
|
||
|
|
* %rdi: round key array, CTX
|
||
|
|
* %rsi: dst (8 blocks)
|
||
|
|
* %rdx: src (8 blocks)
|
||
|
|
* %rcx: iv
|
||
|
|
*/
|
||
|
|
FRAME_BEGIN
|
||
|
|
|
||
|
|
vmovdqu (0 * 16)(%rdx), RA0;
|
||
|
|
vmovdqu (1 * 16)(%rdx), RA1;
|
||
|
|
vmovdqu (2 * 16)(%rdx), RA2;
|
||
|
|
vmovdqu (3 * 16)(%rdx), RA3;
|
||
|
|
vmovdqu (4 * 16)(%rdx), RB0;
|
||
|
|
vmovdqu (5 * 16)(%rdx), RB1;
|
||
|
|
vmovdqu (6 * 16)(%rdx), RB2;
|
||
|
|
vmovdqu (7 * 16)(%rdx), RB3;
|
||
|
|
|
||
|
|
call __sm4_crypt_blk8;
|
||
|
|
|
||
|
|
vmovdqu (7 * 16)(%rdx), RNOT;
|
||
|
|
vpxor (%rcx), RA0, RA0;
|
||
|
|
vpxor (0 * 16)(%rdx), RA1, RA1;
|
||
|
|
vpxor (1 * 16)(%rdx), RA2, RA2;
|
||
|
|
vpxor (2 * 16)(%rdx), RA3, RA3;
|
||
|
|
vpxor (3 * 16)(%rdx), RB0, RB0;
|
||
|
|
vpxor (4 * 16)(%rdx), RB1, RB1;
|
||
|
|
vpxor (5 * 16)(%rdx), RB2, RB2;
|
||
|
|
vpxor (6 * 16)(%rdx), RB3, RB3;
|
||
|
|
vmovdqu RNOT, (%rcx); /* store new IV */
|
||
|
|
|
||
|
|
vmovdqu RA0, (0 * 16)(%rsi);
|
||
|
|
vmovdqu RA1, (1 * 16)(%rsi);
|
||
|
|
vmovdqu RA2, (2 * 16)(%rsi);
|
||
|
|
vmovdqu RA3, (3 * 16)(%rsi);
|
||
|
|
vmovdqu RB0, (4 * 16)(%rsi);
|
||
|
|
vmovdqu RB1, (5 * 16)(%rsi);
|
||
|
|
vmovdqu RB2, (6 * 16)(%rsi);
|
||
|
|
vmovdqu RB3, (7 * 16)(%rsi);
|
||
|
|
|
||
|
|
vzeroall;
|
||
|
|
FRAME_END
|
||
|
|
RET;
|
||
|
|
SYM_FUNC_END(sm4_aesni_avx_cbc_dec_blk8)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void sm4_aesni_avx_cfb_dec_blk8(const u32 *rk, u8 *dst,
|
||
|
|
* const u8 *src, u8 *iv)
|
||
|
|
*/
|
||
|
|
.align 8
|
||
|
|
SYM_TYPED_FUNC_START(sm4_aesni_avx_cfb_dec_blk8)
|
||
|
|
/* input:
|
||
|
|
* %rdi: round key array, CTX
|
||
|
|
* %rsi: dst (8 blocks)
|
||
|
|
* %rdx: src (8 blocks)
|
||
|
|
* %rcx: iv
|
||
|
|
*/
|
||
|
|
FRAME_BEGIN
|
||
|
|
|
||
|
|
/* Load input */
|
||
|
|
vmovdqu (%rcx), RA0;
|
||
|
|
vmovdqu 0 * 16(%rdx), RA1;
|
||
|
|
vmovdqu 1 * 16(%rdx), RA2;
|
||
|
|
vmovdqu 2 * 16(%rdx), RA3;
|
||
|
|
vmovdqu 3 * 16(%rdx), RB0;
|
||
|
|
vmovdqu 4 * 16(%rdx), RB1;
|
||
|
|
vmovdqu 5 * 16(%rdx), RB2;
|
||
|
|
vmovdqu 6 * 16(%rdx), RB3;
|
||
|
|
|
||
|
|
/* Update IV */
|
||
|
|
vmovdqu 7 * 16(%rdx), RNOT;
|
||
|
|
vmovdqu RNOT, (%rcx);
|
||
|
|
|
||
|
|
call __sm4_crypt_blk8;
|
||
|
|
|
||
|
|
vpxor (0 * 16)(%rdx), RA0, RA0;
|
||
|
|
vpxor (1 * 16)(%rdx), RA1, RA1;
|
||
|
|
vpxor (2 * 16)(%rdx), RA2, RA2;
|
||
|
|
vpxor (3 * 16)(%rdx), RA3, RA3;
|
||
|
|
vpxor (4 * 16)(%rdx), RB0, RB0;
|
||
|
|
vpxor (5 * 16)(%rdx), RB1, RB1;
|
||
|
|
vpxor (6 * 16)(%rdx), RB2, RB2;
|
||
|
|
vpxor (7 * 16)(%rdx), RB3, RB3;
|
||
|
|
|
||
|
|
vmovdqu RA0, (0 * 16)(%rsi);
|
||
|
|
vmovdqu RA1, (1 * 16)(%rsi);
|
||
|
|
vmovdqu RA2, (2 * 16)(%rsi);
|
||
|
|
vmovdqu RA3, (3 * 16)(%rsi);
|
||
|
|
vmovdqu RB0, (4 * 16)(%rsi);
|
||
|
|
vmovdqu RB1, (5 * 16)(%rsi);
|
||
|
|
vmovdqu RB2, (6 * 16)(%rsi);
|
||
|
|
vmovdqu RB3, (7 * 16)(%rsi);
|
||
|
|
|
||
|
|
vzeroall;
|
||
|
|
FRAME_END
|
||
|
|
RET;
|
||
|
|
SYM_FUNC_END(sm4_aesni_avx_cfb_dec_blk8)
|