502 lines
13 KiB
C
502 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Performance counter support for PPC970-family processors.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*/
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#include <linux/string.h>
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#include <linux/perf_event.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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#include "internal.h"
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/*
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* Bits in event code for PPC970
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*/
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#define PM_PMC_SH 12 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0xf
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#define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */
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#define PM_UNIT_MSK 0xf
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#define PM_SPCSEL_SH 6
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#define PM_SPCSEL_MSK 3
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#define PM_BYTE_SH 4 /* Byte number of event bus to use */
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#define PM_BYTE_MSK 3
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#define PM_PMCSEL_MSK 0xf
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/* Values in PM_UNIT field */
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#define PM_NONE 0
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#define PM_FPU 1
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#define PM_VPU 2
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#define PM_ISU 3
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#define PM_IFU 4
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#define PM_IDU 5
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#define PM_STS 6
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#define PM_LSU0 7
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#define PM_LSU1U 8
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#define PM_LSU1L 9
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#define PM_LASTUNIT 9
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/*
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* Bits in MMCR0 for PPC970
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*/
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#define MMCR0_PMC1SEL_SH 8
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#define MMCR0_PMC2SEL_SH 1
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#define MMCR_PMCSEL_MSK 0x1f
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/*
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* Bits in MMCR1 for PPC970
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*/
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#define MMCR1_TTM0SEL_SH 62
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#define MMCR1_TTM1SEL_SH 59
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#define MMCR1_TTM3SEL_SH 53
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#define MMCR1_TTMSEL_MSK 3
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#define MMCR1_TD_CP_DBG0SEL_SH 50
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#define MMCR1_TD_CP_DBG1SEL_SH 48
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#define MMCR1_TD_CP_DBG2SEL_SH 46
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#define MMCR1_TD_CP_DBG3SEL_SH 44
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#define MMCR1_PMC1_ADDER_SEL_SH 39
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#define MMCR1_PMC2_ADDER_SEL_SH 38
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#define MMCR1_PMC6_ADDER_SEL_SH 37
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#define MMCR1_PMC5_ADDER_SEL_SH 36
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#define MMCR1_PMC8_ADDER_SEL_SH 35
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#define MMCR1_PMC7_ADDER_SEL_SH 34
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#define MMCR1_PMC3_ADDER_SEL_SH 33
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#define MMCR1_PMC4_ADDER_SEL_SH 32
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#define MMCR1_PMC3SEL_SH 27
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#define MMCR1_PMC4SEL_SH 22
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#define MMCR1_PMC5SEL_SH 17
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#define MMCR1_PMC6SEL_SH 12
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#define MMCR1_PMC7SEL_SH 7
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#define MMCR1_PMC8SEL_SH 2
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static short mmcr1_adder_bits[8] = {
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MMCR1_PMC1_ADDER_SEL_SH,
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MMCR1_PMC2_ADDER_SEL_SH,
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MMCR1_PMC3_ADDER_SEL_SH,
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MMCR1_PMC4_ADDER_SEL_SH,
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MMCR1_PMC5_ADDER_SEL_SH,
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MMCR1_PMC6_ADDER_SEL_SH,
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MMCR1_PMC7_ADDER_SEL_SH,
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MMCR1_PMC8_ADDER_SEL_SH
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};
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/*
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* Layout of constraint bits:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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* <><><>[ >[ >[ >< >< >< >< ><><><><><><><><>
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* SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
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*
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* SP - SPCSEL constraint
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* 48-49: SPCSEL value 0x3_0000_0000_0000
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*
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* T0 - TTM0 constraint
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* 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
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*
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* T1 - TTM1 constraint
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* 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
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*
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* UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
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* 43: UC3 error 0x0800_0000_0000
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* 42: FPU|IFU|VPU events needed 0x0400_0000_0000
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* 41: ISU events needed 0x0200_0000_0000
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* 40: IDU|STS events needed 0x0100_0000_0000
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*
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* PS1
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* 39: PS1 error 0x0080_0000_0000
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* 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
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*
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* PS2
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* 35: PS2 error 0x0008_0000_0000
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* 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
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*
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* B0
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* 28-31: Byte 0 event source 0xf000_0000
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* Encoding as for the event code
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*
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* B1, B2, B3
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* 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
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*
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* P1
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* 15: P1 error 0x8000
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* 14-15: Count of events needing PMC1
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*
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* P2..P8
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* 0-13: Count of events needing PMC2..PMC8
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*/
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static unsigned char direct_marked_event[8] = {
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(1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
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(1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
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(1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
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(1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
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(1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
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(1<<3) | (1<<4) | (1<<5),
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/* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
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(1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
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(1<<4) /* PMC8: PM_MRK_LSU_FIN */
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};
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/*
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* Returns 1 if event counts things relating to marked instructions
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* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
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*/
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static int p970_marked_instr_event(u64 event)
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{
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int pmc, psel, unit, byte, bit;
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unsigned int mask;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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psel = event & PM_PMCSEL_MSK;
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if (pmc) {
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if (direct_marked_event[pmc - 1] & (1 << psel))
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return 1;
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if (psel == 0) /* add events */
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bit = (pmc <= 4)? pmc - 1: 8 - pmc;
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else if (psel == 7 || psel == 13) /* decode events */
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bit = 4;
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else
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return 0;
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} else
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bit = psel;
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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mask = 0;
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switch (unit) {
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case PM_VPU:
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mask = 0x4c; /* byte 0 bits 2,3,6 */
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break;
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case PM_LSU0:
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/* byte 2 bits 0,2,3,4,6; all of byte 1 */
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mask = 0x085dff00;
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break;
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case PM_LSU1L:
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mask = 0x50 << 24; /* byte 3 bits 4,6 */
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break;
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}
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return (mask >> (byte * 8 + bit)) & 1;
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}
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/* Masks and values for using events from the various units */
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static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
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[PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
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[PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
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[PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
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[PM_IFU] = { 0xc80000000000ull, 0x840000000000ull },
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[PM_IDU] = { 0x380000000000ull, 0x010000000000ull },
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[PM_STS] = { 0x380000000000ull, 0x310000000000ull },
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};
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static int p970_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp, u64 event_config1 __maybe_unused)
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{
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int pmc, byte, unit, sh, spcsel;
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unsigned long mask = 0, value = 0;
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int grp = -1;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 8)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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grp = ((pmc - 1) >> 1) & 1;
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}
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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if (unit) {
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if (unit > PM_LASTUNIT)
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return -1;
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mask |= unit_cons[unit][0];
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value |= unit_cons[unit][1];
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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/*
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* Bus events on bytes 0 and 2 can be counted
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* on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
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*/
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if (!pmc)
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grp = byte & 1;
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/* Set byte lane select field */
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mask |= 0xfULL << (28 - 4 * byte);
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value |= (unsigned long)unit << (28 - 4 * byte);
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}
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if (grp == 0) {
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/* increment PMC1/2/5/6 field */
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mask |= 0x8000000000ull;
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value |= 0x1000000000ull;
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} else if (grp == 1) {
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/* increment PMC3/4/7/8 field */
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mask |= 0x800000000ull;
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value |= 0x100000000ull;
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}
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spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
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if (spcsel) {
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mask |= 3ull << 48;
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value |= (unsigned long)spcsel << 48;
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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alt[0] = event;
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/* 2 alternatives for LSU empty */
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if (event == 0x2002 || event == 0x3002) {
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alt[1] = event ^ 0x1000;
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return 2;
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}
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return 1;
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}
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static int p970_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[],
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u32 flags __maybe_unused)
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{
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unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
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unsigned int pmc, unit, byte, psel;
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unsigned int ttm, grp;
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unsigned int pmc_inuse = 0;
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unsigned int pmc_grp_use[2];
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unsigned char busbyte[4];
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unsigned char unituse[16];
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unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
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unsigned char ttmuse[2];
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unsigned char pmcsel[8];
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int i;
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int spcsel;
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if (n_ev > 8)
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return -1;
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/* First pass to count resource use */
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pmc_grp_use[0] = pmc_grp_use[1] = 0;
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memset(busbyte, 0, sizeof(busbyte));
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memset(unituse, 0, sizeof(unituse));
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1;
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pmc_inuse |= 1 << (pmc - 1);
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/* count 1/2/5/6 vs 3/4/7/8 use */
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++pmc_grp_use[((pmc - 1) >> 1) & 1];
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}
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unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
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byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
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if (unit) {
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if (unit > PM_LASTUNIT)
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return -1;
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if (!pmc)
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++pmc_grp_use[byte & 1];
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if (busbyte[byte] && busbyte[byte] != unit)
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return -1;
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busbyte[byte] = unit;
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unituse[unit] = 1;
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}
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}
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if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
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return -1;
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/*
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* Assign resources and set multiplexer selects.
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*
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* PM_ISU can go either on TTM0 or TTM1, but that's the only
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* choice we have to deal with.
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*/
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if (unituse[PM_ISU] &
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(unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
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unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */
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/* Set TTM[01]SEL fields. */
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ttmuse[0] = ttmuse[1] = 0;
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for (i = PM_FPU; i <= PM_STS; ++i) {
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if (!unituse[i])
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continue;
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ttm = unitmap[i];
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++ttmuse[(ttm >> 2) & 1];
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mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
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}
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/* Check only one unit per TTMx */
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if (ttmuse[0] > 1 || ttmuse[1] > 1)
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return -1;
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/* Set byte lane select fields and TTM3SEL. */
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for (byte = 0; byte < 4; ++byte) {
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unit = busbyte[byte];
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if (!unit)
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continue;
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if (unit <= PM_STS)
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ttm = (unitmap[unit] >> 2) & 1;
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|
else if (unit == PM_LSU0)
|
||
|
|
ttm = 2;
|
||
|
|
else {
|
||
|
|
ttm = 3;
|
||
|
|
if (unit == PM_LSU1L && byte >= 2)
|
||
|
|
mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
|
||
|
|
}
|
||
|
|
mmcr1 |= (unsigned long)ttm
|
||
|
|
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
|
||
|
|
memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */
|
||
|
|
for (i = 0; i < n_ev; ++i) {
|
||
|
|
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
||
|
|
unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
|
||
|
|
byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
|
||
|
|
psel = event[i] & PM_PMCSEL_MSK;
|
||
|
|
if (!pmc) {
|
||
|
|
/* Bus event or any-PMC direct event */
|
||
|
|
if (unit)
|
||
|
|
psel |= 0x10 | ((byte & 2) << 2);
|
||
|
|
else
|
||
|
|
psel |= 8;
|
||
|
|
for (pmc = 0; pmc < 8; ++pmc) {
|
||
|
|
if (pmc_inuse & (1 << pmc))
|
||
|
|
continue;
|
||
|
|
grp = (pmc >> 1) & 1;
|
||
|
|
if (unit) {
|
||
|
|
if (grp == (byte & 1))
|
||
|
|
break;
|
||
|
|
} else if (pmc_grp_use[grp] < 4) {
|
||
|
|
++pmc_grp_use[grp];
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
pmc_inuse |= 1 << pmc;
|
||
|
|
} else {
|
||
|
|
/* Direct event */
|
||
|
|
--pmc;
|
||
|
|
if (psel == 0 && (byte & 2))
|
||
|
|
/* add events on higher-numbered bus */
|
||
|
|
mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
|
||
|
|
}
|
||
|
|
pmcsel[pmc] = psel;
|
||
|
|
hwc[i] = pmc;
|
||
|
|
spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
|
||
|
|
mmcr1 |= spcsel;
|
||
|
|
if (p970_marked_instr_event(event[i]))
|
||
|
|
mmcra |= MMCRA_SAMPLE_ENABLE;
|
||
|
|
}
|
||
|
|
for (pmc = 0; pmc < 2; ++pmc)
|
||
|
|
mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
|
||
|
|
for (; pmc < 8; ++pmc)
|
||
|
|
mmcr1 |= (unsigned long)pmcsel[pmc]
|
||
|
|
<< (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
|
||
|
|
if (pmc_inuse & 1)
|
||
|
|
mmcr0 |= MMCR0_PMC1CE;
|
||
|
|
if (pmc_inuse & 0xfe)
|
||
|
|
mmcr0 |= MMCR0_PMCjCE;
|
||
|
|
|
||
|
|
mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
|
||
|
|
|
||
|
|
/* Return MMCRx values */
|
||
|
|
mmcr->mmcr0 = mmcr0;
|
||
|
|
mmcr->mmcr1 = mmcr1;
|
||
|
|
mmcr->mmcra = mmcra;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void p970_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
||
|
|
{
|
||
|
|
int shift;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Setting the PMCxSEL field to 0x08 disables PMC x.
|
||
|
|
*/
|
||
|
|
if (pmc <= 1) {
|
||
|
|
shift = MMCR0_PMC1SEL_SH - 7 * pmc;
|
||
|
|
mmcr->mmcr0 = (mmcr->mmcr0 & ~(0x1fUL << shift)) | (0x08UL << shift);
|
||
|
|
} else {
|
||
|
|
shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
|
||
|
|
mmcr->mmcr1 = (mmcr->mmcr1 & ~(0x1fUL << shift)) | (0x08UL << shift);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ppc970_generic_events[] = {
|
||
|
|
[PERF_COUNT_HW_CPU_CYCLES] = 7,
|
||
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = 1,
|
||
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */
|
||
|
|
[PERF_COUNT_HW_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */
|
||
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */
|
||
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
|
||
|
|
};
|
||
|
|
|
||
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Table of generalized cache-related events.
|
||
|
|
* 0 means not supported, -1 means nonsensical, other values
|
||
|
|
* are event codes.
|
||
|
|
*/
|
||
|
|
static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
||
|
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0x8810, 0x3810 },
|
||
|
|
[C(OP_WRITE)] = { 0x7810, 0x813 },
|
||
|
|
[C(OP_PREFETCH)] = { 0x731, 0 },
|
||
|
|
},
|
||
|
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0, 0 },
|
||
|
|
[C(OP_WRITE)] = { -1, -1 },
|
||
|
|
[C(OP_PREFETCH)] = { 0, 0 },
|
||
|
|
},
|
||
|
|
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0, 0 },
|
||
|
|
[C(OP_WRITE)] = { 0, 0 },
|
||
|
|
[C(OP_PREFETCH)] = { 0x733, 0 },
|
||
|
|
},
|
||
|
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0, 0x704 },
|
||
|
|
[C(OP_WRITE)] = { -1, -1 },
|
||
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||
|
|
},
|
||
|
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0, 0x700 },
|
||
|
|
[C(OP_WRITE)] = { -1, -1 },
|
||
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||
|
|
},
|
||
|
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { 0x431, 0x327 },
|
||
|
|
[C(OP_WRITE)] = { -1, -1 },
|
||
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||
|
|
},
|
||
|
|
[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
|
||
|
|
[C(OP_READ)] = { -1, -1 },
|
||
|
|
[C(OP_WRITE)] = { -1, -1 },
|
||
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct power_pmu ppc970_pmu = {
|
||
|
|
.name = "PPC970/FX/MP",
|
||
|
|
.n_counter = 8,
|
||
|
|
.max_alternatives = 2,
|
||
|
|
.add_fields = 0x001100005555ull,
|
||
|
|
.test_adder = 0x013300000000ull,
|
||
|
|
.compute_mmcr = p970_compute_mmcr,
|
||
|
|
.get_constraint = p970_get_constraint,
|
||
|
|
.get_alternatives = p970_get_alternatives,
|
||
|
|
.disable_pmc = p970_disable_pmc,
|
||
|
|
.n_generic = ARRAY_SIZE(ppc970_generic_events),
|
||
|
|
.generic_events = ppc970_generic_events,
|
||
|
|
.cache_events = &ppc970_cache_events,
|
||
|
|
.flags = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING,
|
||
|
|
};
|
||
|
|
|
||
|
|
int __init init_ppc970_pmu(void)
|
||
|
|
{
|
||
|
|
unsigned int pvr = mfspr(SPRN_PVR);
|
||
|
|
|
||
|
|
if (PVR_VER(pvr) != PVR_970 && PVR_VER(pvr) != PVR_970MP &&
|
||
|
|
PVR_VER(pvr) != PVR_970FX && PVR_VER(pvr) != PVR_970GX)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
return register_power_pmu(&ppc970_pmu);
|
||
|
|
}
|