124 lines
2.7 KiB
C
124 lines
2.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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*/
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/prom.h>
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#include <lantiq.h>
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#include "prom.h"
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#include "clk.h"
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/* access to the ebu needs to be locked between different drivers */
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DEFINE_SPINLOCK(ebu_lock);
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EXPORT_SYMBOL_GPL(ebu_lock);
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/*
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* This is needed by the VPE loader code, just set it to 0 and assume
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* that the firmware hardcodes this value to something useful.
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*/
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unsigned long physical_memsize = 0L;
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/*
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* this struct is filled by the soc specific detection code and holds
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* information about the specific soc type, revision and name
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*/
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static struct ltq_soc_info soc_info;
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/*
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* These structs are used to override vsmp_init_secondary()
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*/
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#if defined(CONFIG_MIPS_MT_SMP)
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extern const struct plat_smp_ops vsmp_smp_ops;
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static struct plat_smp_ops lantiq_smp_ops;
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#endif
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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}
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int ltq_soc_type(void)
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{
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return soc_info.type;
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}
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static void __init prom_init_cmdline(void)
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{
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int argc = fw_arg0;
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char **argv = (char **) KSEG1ADDR(fw_arg1);
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int i;
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arcs_cmdline[0] = '\0';
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for (i = 0; i < argc; i++) {
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char *p = (char *) KSEG1ADDR(argv[i]);
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if (CPHYSADDR(p) && *p) {
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strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
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strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
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}
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}
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}
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void __init plat_mem_setup(void)
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{
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void *dtb;
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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set_io_port_base((unsigned long) KSEG1);
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dtb = get_fdt();
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if (dtb == NULL)
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panic("no dtb found");
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/*
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* Load the devicetree. This causes the chosen node to be
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* parsed resulting in our memory appearing
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*/
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__dt_setup_arch(dtb);
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}
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#if defined(CONFIG_MIPS_MT_SMP)
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static void lantiq_init_secondary(void)
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{
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/*
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* MIPS CPU startup function vsmp_init_secondary() will only
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* enable some of the interrupts for the second CPU/VPE.
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*/
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set_c0_status(ST0_IM);
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}
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#endif
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void __init prom_init(void)
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{
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/* call the soc specific detetcion code and get it to fill soc_info */
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ltq_soc_detect(&soc_info);
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snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
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soc_info.name, soc_info.rev_type);
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soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
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pr_info("SoC: %s\n", soc_info.sys_type);
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prom_init_cmdline();
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#if defined(CONFIG_MIPS_MT_SMP)
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if (cpu_has_mipsmt) {
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lantiq_smp_ops = vsmp_smp_ops;
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lantiq_smp_ops.init_secondary = lantiq_init_secondary;
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register_smp_ops(&lantiq_smp_ops);
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}
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#endif
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}
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