308 lines
7.1 KiB
ArmAsm
308 lines
7.1 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Hypervisor stub
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/el2_setup.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/ptrace.h>
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#include <asm/virt.h>
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// Warning, hardcoded register allocation
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// This will clobber x1 and x2, and expect x1 to contain
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// the id register value as read from the HW
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.macro __check_override idreg, fld, width, pass, fail
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ubfx x1, x1, #\fld, #\width
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cbz x1, \fail
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adr_l x1, \idreg\()_override
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ldr x2, [x1, FTR_OVR_VAL_OFFSET]
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ldr x1, [x1, FTR_OVR_MASK_OFFSET]
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ubfx x2, x2, #\fld, #\width
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ubfx x1, x1, #\fld, #\width
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cmp x1, xzr
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and x2, x2, x1
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csinv x2, x2, xzr, ne
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cbnz x2, \pass
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b \fail
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.endm
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.macro check_override idreg, fld, pass, fail
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mrs x1, \idreg\()_el1
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__check_override \idreg \fld 4 \pass \fail
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.endm
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.text
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.pushsection .hyp.text, "ax"
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.align 11
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SYM_CODE_START(__hyp_stub_vectors)
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ventry el2_sync_invalid // Synchronous EL2t
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ventry el2_irq_invalid // IRQ EL2t
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ventry el2_fiq_invalid // FIQ EL2t
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ventry el2_error_invalid // Error EL2t
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ventry elx_sync // Synchronous EL2h
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ventry el2_irq_invalid // IRQ EL2h
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ventry el2_fiq_invalid // FIQ EL2h
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ventry el2_error_invalid // Error EL2h
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ventry elx_sync // Synchronous 64-bit EL1
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ventry el1_irq_invalid // IRQ 64-bit EL1
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ventry el1_fiq_invalid // FIQ 64-bit EL1
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ventry el1_error_invalid // Error 64-bit EL1
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ventry el1_sync_invalid // Synchronous 32-bit EL1
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ventry el1_irq_invalid // IRQ 32-bit EL1
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ventry el1_fiq_invalid // FIQ 32-bit EL1
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ventry el1_error_invalid // Error 32-bit EL1
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SYM_CODE_END(__hyp_stub_vectors)
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.align 11
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SYM_CODE_START_LOCAL(elx_sync)
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cmp x0, #HVC_SET_VECTORS
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b.ne 1f
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msr vbar_el2, x1
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b 9f
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1: cmp x0, #HVC_FINALISE_EL2
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b.eq __finalise_el2
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2: cmp x0, #HVC_SOFT_RESTART
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b.ne 3f
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mov x0, x2
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mov x2, x4
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mov x4, x1
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mov x1, x3
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br x4 // no return
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3: cmp x0, #HVC_RESET_VECTORS
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beq 9f // Nothing to reset!
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/* Someone called kvm_call_hyp() against the hyp-stub... */
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mov_q x0, HVC_STUB_ERR
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eret
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9: mov x0, xzr
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eret
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SYM_CODE_END(elx_sync)
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SYM_CODE_START_LOCAL(__finalise_el2)
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check_override id_aa64pfr0 ID_AA64PFR0_EL1_SVE_SHIFT .Linit_sve .Lskip_sve
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.Linit_sve: /* SVE register access */
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mrs x0, cptr_el2 // Disable SVE traps
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bic x0, x0, #CPTR_EL2_TZ
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msr cptr_el2, x0
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isb
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mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
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msr_s SYS_ZCR_EL2, x1 // length for EL1.
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.Lskip_sve:
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check_override id_aa64pfr1 ID_AA64PFR1_EL1_SME_SHIFT .Linit_sme .Lskip_sme
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.Linit_sme: /* SME register access and priority mapping */
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mrs x0, cptr_el2 // Disable SME traps
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bic x0, x0, #CPTR_EL2_TSM
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msr cptr_el2, x0
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isb
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mrs x1, sctlr_el2
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orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
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msr sctlr_el2, x1
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isb
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mov x0, #0 // SMCR controls
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// Full FP in SM?
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mrs_s x1, SYS_ID_AA64SMFR0_EL1
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__check_override id_aa64smfr0 ID_AA64SMFR0_EL1_FA64_SHIFT 1 .Linit_sme_fa64 .Lskip_sme_fa64
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.Linit_sme_fa64:
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orr x0, x0, SMCR_ELx_FA64_MASK
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.Lskip_sme_fa64:
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orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
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msr_s SYS_SMCR_EL2, x0 // length for EL1.
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mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
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ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
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cbz x1, .Lskip_sme
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msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
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mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
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ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
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cbz x1, .Lskip_sme
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mrs_s x1, SYS_HCRX_EL2
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orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
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msr_s SYS_HCRX_EL2, x1
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.Lskip_sme:
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// nVHE? No way! Give me the real thing!
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// Sanity check: MMU *must* be off
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mrs x1, sctlr_el2
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tbnz x1, #0, 1f
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// Needs to be VHE capable, obviously
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check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
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1: mov_q x0, HVC_STUB_ERR
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eret
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2:
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// Engage the VHE magic!
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mov_q x0, HCR_HOST_VHE_FLAGS
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msr hcr_el2, x0
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isb
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// Use the EL1 allocated stack, per-cpu offset
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mrs x0, sp_el1
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mov sp, x0
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mrs x0, tpidr_el1
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msr tpidr_el2, x0
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// FP configuration, vectors
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mrs_s x0, SYS_CPACR_EL12
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msr cpacr_el1, x0
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mrs_s x0, SYS_VBAR_EL12
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msr vbar_el1, x0
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// Use EL2 translations for SPE & TRBE and disable access from EL1
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mrs x0, mdcr_el2
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bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
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bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
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msr mdcr_el2, x0
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// Transfer the MM state from EL1 to EL2
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mrs_s x0, SYS_TCR_EL12
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msr tcr_el1, x0
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mrs_s x0, SYS_TTBR0_EL12
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msr ttbr0_el1, x0
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mrs_s x0, SYS_TTBR1_EL12
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msr ttbr1_el1, x0
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mrs_s x0, SYS_MAIR_EL12
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msr mair_el1, x0
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isb
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// Hack the exception return to stay at EL2
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mrs x0, spsr_el1
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and x0, x0, #~PSR_MODE_MASK
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mov x1, #PSR_MODE_EL2h
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orr x0, x0, x1
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msr spsr_el1, x0
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b enter_vhe
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SYM_CODE_END(__finalise_el2)
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// At the point where we reach enter_vhe(), we run with
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// the MMU off (which is enforced by __finalise_el2()).
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// We thus need to be in the idmap, or everything will
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// explode when enabling the MMU.
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.pushsection .idmap.text, "ax"
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SYM_CODE_START_LOCAL(enter_vhe)
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// Invalidate TLBs before enabling the MMU
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tlbi vmalle1
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dsb nsh
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isb
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// Enable the EL2 S1 MMU, as set up from EL1
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mrs_s x0, SYS_SCTLR_EL12
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set_sctlr_el1 x0
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// Disable the EL1 S1 MMU for a good measure
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mov_q x0, INIT_SCTLR_EL1_MMU_OFF
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msr_s SYS_SCTLR_EL12, x0
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mov x0, xzr
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eret
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SYM_CODE_END(enter_vhe)
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.popsection
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.macro invalid_vector label
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SYM_CODE_START_LOCAL(\label)
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b \label
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SYM_CODE_END(\label)
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.endm
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invalid_vector el2_sync_invalid
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invalid_vector el2_irq_invalid
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invalid_vector el2_fiq_invalid
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invalid_vector el2_error_invalid
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invalid_vector el1_sync_invalid
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invalid_vector el1_irq_invalid
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invalid_vector el1_fiq_invalid
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invalid_vector el1_error_invalid
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.popsection
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/*
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* __hyp_set_vectors: Call this after boot to set the initial hypervisor
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* vectors as part of hypervisor installation. On an SMP system, this should
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* be called on each CPU.
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*
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* x0 must be the physical address of the new vector table, and must be
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* 2KB aligned.
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*
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* Before calling this, you must check that the stub hypervisor is installed
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* everywhere, by waiting for any secondary CPUs to be brought up and then
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* checking that is_hyp_mode_available() is true.
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*
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* If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
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* something else went wrong... in such cases, trying to install a new
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* hypervisor is unlikely to work as desired.
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*
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* When you call into your shiny new hypervisor, sp_el2 will contain junk,
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* so you will need to set that to something sensible at the new hypervisor's
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* initialisation entry point.
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*/
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SYM_FUNC_START(__hyp_set_vectors)
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mov x1, x0
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mov x0, #HVC_SET_VECTORS
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hvc #0
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ret
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SYM_FUNC_END(__hyp_set_vectors)
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SYM_FUNC_START(__hyp_reset_vectors)
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mov x0, #HVC_RESET_VECTORS
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hvc #0
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ret
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SYM_FUNC_END(__hyp_reset_vectors)
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/*
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* Entry point to finalise EL2 and switch to VHE if deemed capable
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*
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* w0: boot mode, as returned by init_kernel_el()
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*/
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SYM_FUNC_START(finalise_el2)
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// Need to have booted at EL2
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cmp w0, #BOOT_CPU_MODE_EL2
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b.ne 1f
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// and still be at EL1
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL1
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b.ne 1f
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mov x0, #HVC_FINALISE_EL2
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hvc #0
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1:
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ret
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SYM_FUNC_END(finalise_el2)
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