108 lines
2.0 KiB
Plaintext
108 lines
2.0 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
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*/
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/ {
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model = "Khadas VIM3";
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vddcpu_a: regulator-vddcpu-a {
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/*
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* MP8756GD Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_A";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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pwm-supply = <&dc_in>;
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pwms = <&pwm_ab 0 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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vddcpu_b: regulator-vddcpu-b {
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/*
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* Silergy SY8030DEC Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU_B";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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pwm-supply = <&vsys_3v3>;
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pwms = <&pwm_AO_cd 1 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table_0>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu100 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu101 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu102 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&cpu103 {
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cpu-supply = <&vddcpu_a>;
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operating-points-v2 = <&cpub_opp_table_1>;
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clocks = <&clkc CLKID_CPUB_CLK>;
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clock-latency = <50000>;
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};
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&pwm_ab {
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pinctrl-0 = <&pwm_a_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin0";
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status = "okay";
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};
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&pwm_AO_cd {
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pinctrl-0 = <&pwm_ao_d_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin1";
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status = "okay";
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};
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