71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2012 Calxeda, Inc.
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*/
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#ifndef _ASM_ARM_PERCPU_H_
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#define _ASM_ARM_PERCPU_H_
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#include <asm/insn.h>
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register unsigned long current_stack_pointer asm ("sp");
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/*
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* Same as asm-generic/percpu.h, except that we store the per cpu offset
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* in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
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*/
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#ifdef CONFIG_SMP
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static inline void set_my_cpu_offset(unsigned long off)
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{
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extern unsigned int smp_on_up;
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if (IS_ENABLED(CONFIG_CPU_V6) && !smp_on_up)
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return;
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/* Set TPIDRPRW */
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asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
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}
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static __always_inline unsigned long __my_cpu_offset(void)
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{
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unsigned long off;
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/*
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* Read TPIDRPRW.
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* We want to allow caching the value, so avoid using volatile and
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* instead use a fake stack read to hazard against barrier().
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*/
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asm("0: mrc p15, 0, %0, c13, c0, 4 \n\t"
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#ifdef CONFIG_CPU_V6
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"1: \n\t"
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" .subsection 1 \n\t"
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#if defined(CONFIG_ARM_HAS_GROUP_RELOCS) && \
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!(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
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"2: " LOAD_SYM_ARMV6(%0, __per_cpu_offset) " \n\t"
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" b 1b \n\t"
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#else
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"2: ldr %0, 3f \n\t"
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" ldr %0, [%0] \n\t"
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" b 1b \n\t"
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"3: .long __per_cpu_offset \n\t"
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#endif
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" .previous \n\t"
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" .pushsection \".alt.smp.init\", \"a\" \n\t"
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" .long 0b - . \n\t"
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" b . + (2b - 0b) \n\t"
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" .popsection \n\t"
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#endif
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: "=r" (off)
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: "Q" (*(const unsigned long *)current_stack_pointer));
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return off;
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}
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#define __my_cpu_offset __my_cpu_offset()
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#else
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#define set_my_cpu_offset(x) do {} while(0)
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#endif /* CONFIG_SMP */
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#include <asm-generic/percpu.h>
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#endif /* _ASM_ARM_PERCPU_H_ */
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