351 lines
11 KiB
YAML
351 lines
11 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Vidya Sagar <vidyas@nvidia.com>
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description: |
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
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inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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the controller instances are dual mode where in they can work either in
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Root Port mode or Endpoint mode but one at a time.
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See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
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tree bindings.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-pcie
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- nvidia,tegra234-pcie
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reg:
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items:
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- description: controller's application logic registers
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- description: configuration registers
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- description: iATU and DMA registers. This is where the iATU (internal
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Address Translation Unit) registers of the PCIe core are made
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available for software access.
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- description: aperture where the Root Port's own configuration
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registers are available.
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reg-names:
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items:
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- const: appl
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- const: config
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- const: atu_dma
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- const: dbi
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interrupts:
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items:
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- description: controller interrupt
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- description: MSI interrupt
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interrupt-names:
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items:
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- const: intr
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- const: msi
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clocks:
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items:
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- description: module clock
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clock-names:
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items:
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- const: core
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resets:
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items:
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- description: APB bus interface reset
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- description: module reset
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reset-names:
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items:
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- const: apb
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- const: core
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phys:
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minItems: 1
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maxItems: 8
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phy-names:
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minItems: 1
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items:
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- const: p2u-0
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- const: p2u-1
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- const: p2u-2
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- const: p2u-3
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- const: p2u-4
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- const: p2u-5
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- const: p2u-6
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- const: p2u-7
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power-domains:
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maxItems: 1
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description: |
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A phandle to the node that controls power to the respective PCIe
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controller and a specifier name for the PCIe controller.
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Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
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Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
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interconnects:
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items:
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- description: memory read client
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- description: memory write client
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interconnect-names:
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items:
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- const: dma-mem # read
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- const: write
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dma-coherent: true
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Must contain a pair of phandles to BPMP controller node followed by
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controller ID. Following are the controller IDs for each controller:
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Tegra194
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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Tegra234
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0 : C0
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1 : C1
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2 : C2
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3 : C3
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4 : C4
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5 : C5
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6 : C6
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7 : C7
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8 : C8
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9 : C9
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10: C10
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items:
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- items:
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- description: phandle to BPMP controller node
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- description: PCIe controller ID
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maximum: 10
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nvidia,update-fc-fixup:
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description: |
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This is a boolean property and needs to be present to improve performance
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when a platform is designed in such a way that it satisfies at least one
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of the following conditions thereby enabling Root Port to exchange
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optimum number of FC (Flow Control) credits with downstream devices:
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NOTE: This is applicable only for Tegra194.
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1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
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2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
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a) speed is Gen-2 and MPS is 256B
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b) speed is >= Gen-3 with any MPS
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$ref: /schemas/types.yaml#/definitions/flag
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nvidia,aspm-cmrt-us:
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description: Common Mode Restore Time for proper operation of ASPM to be
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specified in microseconds
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nvidia,aspm-pwr-on-t-us:
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description: Power On time for proper operation of ASPM to be specified in
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microseconds
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nvidia,aspm-l0s-entrance-latency-us:
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description: ASPM L0s entrance latency to be specified in microseconds
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vddio-pex-ctl-supply:
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description: A phandle to the regulator supply for PCIe side band signals.
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vpcie3v3-supply:
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description: A phandle to the regulator node that supplies 3.3V to the slot
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if the platform has one such slot, e.g., x16 slot owned by C5 controller
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in p2972-0000 platform.
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vpcie12v-supply:
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description: A phandle to the regulator node that supplies 12V to the slot
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if the platform has one such slot, e.g., x16 slot owned by C5 controller
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in p2972-0000 platform.
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nvidia,enable-srns:
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description: |
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This boolean property needs to be present if the controller is
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configured to operate in SRNS (Separate Reference Clocks with No
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Spread-Spectrum Clocking). NOTE: This is applicable only for
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Tegra234.
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$ref: /schemas/types.yaml#/definitions/flag
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nvidia,enable-ext-refclk:
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description: |
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This boolean property needs to be present if the controller is
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configured to use the reference clocking coming in from an external
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clock source instead of using the internal clock source.
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$ref: /schemas/types.yaml#/definitions/flag
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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unevaluatedProperties: false
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required:
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- interrupts
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- interrupt-names
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- interrupt-map
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- interrupt-map-mask
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- vddio-pex-ctl-supply
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- num-lanes
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- phys
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- phy-names
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- nvidia,bpmp
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examples:
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- |
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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bus@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x8 0x0>;
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pcie@14180000 {
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compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
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<0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
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<0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
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reg-names = "appl", "config", "atu_dma", "dbi";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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linux,pci-domain = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
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clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
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<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,bpmp = <&bpmp 0>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
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<0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
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<0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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vpcie3v3-supply = <&vdd_3v3_pcie>;
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vpcie12v-supply = <&vdd_12v_pcie>;
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phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
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<&p2u_hsio_5>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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};
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- |
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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bus@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x8 0x0>;
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pcie@14160000 {
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compatible = "nvidia,tegra234-pcie";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
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reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
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<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
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<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
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reg-names = "appl", "config", "atu_dma", "dbi";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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num-viewport = <8>;
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linux,pci-domain = <4>;
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clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
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clock-names = "core";
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resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
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<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,bpmp = <&bpmp 4>;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
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<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
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<0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
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vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
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phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
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<&p2u_hsio_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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};
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