320 lines
9.4 KiB
YAML
320 lines
9.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Vidya Sagar <vidyas@nvidia.com>
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description: |
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
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inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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of the controller instances are dual mode; they can work either in Root
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Port mode or Endpoint mode but one at a time.
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On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
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On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
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Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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operate in the Endpoint mode because of the way the platform is designed.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-pcie-ep
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- nvidia,tegra234-pcie-ep
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reg:
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items:
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- description: controller's application logic registers
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- description: iATU and DMA registers. This is where the iATU (internal
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Address Translation Unit) registers of the PCIe core are made
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available for software access.
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- description: aperture where the Root Port's own configuration
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registers are available.
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- description: aperture used to map the remote Root Complex address space
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reg-names:
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items:
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- const: appl
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- const: atu_dma
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- const: dbi
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- const: addr_space
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interrupts:
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items:
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- description: controller interrupt
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interrupt-names:
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items:
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- const: intr
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clocks:
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items:
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- description: module clock
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clock-names:
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items:
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- const: core
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resets:
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items:
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- description: APB bus interface reset
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- description: module reset
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reset-names:
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items:
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- const: apb
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- const: core
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reset-gpios:
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description: Must contain a phandle to a GPIO controller followed by GPIO
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that is being used as PERST input signal. Please refer to pci.txt.
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phys:
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minItems: 1
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maxItems: 8
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phy-names:
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minItems: 1
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items:
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- const: p2u-0
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- const: p2u-1
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- const: p2u-2
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- const: p2u-3
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- const: p2u-4
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- const: p2u-5
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- const: p2u-6
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- const: p2u-7
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power-domains:
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maxItems: 1
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description: |
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A phandle to the node that controls power to the respective PCIe
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controller and a specifier name for the PCIe controller.
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Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
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Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
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interconnects:
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items:
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- description: memory read client
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- description: memory write client
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interconnect-names:
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items:
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- const: dma-mem # read
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- const: write
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dma-coherent: true
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Must contain a pair of phandles to BPMP controller node followed by
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controller ID. Following are the controller IDs for each controller:
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Tegra194
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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Tegra234
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0 : C0
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1 : C1
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2 : C2
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3 : C3
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4 : C4
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5 : C5
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6 : C6
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7 : C7
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8 : C8
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9 : C9
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10: C10
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items:
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- items:
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- description: phandle to BPMP controller node
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- description: PCIe controller ID
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maximum: 10
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nvidia,aspm-cmrt-us:
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description: Common Mode Restore Time for proper operation of ASPM to be
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specified in microseconds
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nvidia,aspm-pwr-on-t-us:
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description: Power On time for proper operation of ASPM to be specified in
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microseconds
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nvidia,aspm-l0s-entrance-latency-us:
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description: ASPM L0s entrance latency to be specified in microseconds
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vddio-pex-ctl-supply:
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description: A phandle to the regulator supply for PCIe side band signals
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nvidia,refclk-select-gpios:
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maxItems: 1
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description: GPIO used to enable REFCLK to controller from the host
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nvidia,enable-ext-refclk:
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description: |
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This boolean property needs to be present if the controller is configured
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to receive Reference Clock from the host.
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NOTE: This is applicable only for Tegra234.
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$ref: /schemas/types.yaml#/definitions/flag
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nvidia,enable-srns:
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description: |
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This boolean property needs to be present if the controller is
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configured to operate in SRNS (Separate Reference Clocks with No
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Spread-Spectrum Clocking). NOTE: This is applicable only for
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Tegra234.
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$ref: /schemas/types.yaml#/definitions/flag
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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unevaluatedProperties: false
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required:
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- reset-gpios
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- vddio-pex-ctl-supply
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- num-lanes
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- phys
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- phy-names
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- nvidia,bpmp
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examples:
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- |
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/gpio/tegra194-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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bus@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x8 0x0>;
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pcie-ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep";
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reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
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<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
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<0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
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reg-names = "appl", "atu_dma", "dbi", "addr_space";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
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<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
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reset-names = "apb", "core";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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pinctrl-names = "default";
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pinctrl-0 = <&clkreq_c5_bi_dir_state>;
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nvidia,bpmp = <&bpmp 5>;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
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nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
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GPIO_ACTIVE_HIGH>;
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num-lanes = <8>;
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phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
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<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
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"p2u-5", "p2u-6", "p2u-7";
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};
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};
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- |
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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bus@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x8 0x0>;
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pcie-ep@141a0000 {
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compatible = "nvidia,tegra234-pcie-ep";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
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reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
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<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
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<0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
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reg-names = "appl", "atu_dma", "dbi", "addr_space";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
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clock-names = "core";
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resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
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<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
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reset-names = "apb", "core";
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nvidia,bpmp = <&bpmp 5>;
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nvidia,enable-ext-refclk;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
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reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
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nvidia,refclk-select-gpios = <&gpio_aon
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TEGRA234_AON_GPIO(AA, 4)
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GPIO_ACTIVE_HIGH>;
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num-lanes = <8>;
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phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
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<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
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"p2u-5", "p2u-6", "p2u-7";
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};
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};
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