191 lines
6.1 KiB
C
191 lines
6.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Support for the xscale frame buffer.
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*
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* Author: Jean-Frederic Clere
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* Created: Sep 22, 2003
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* Copyright: jfclere@sinix.net
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*/
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#include <linux/fb.h>
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/*
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* Supported LCD connections
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*
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* bits 0 - 3: for LCD panel type:
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*
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* STN - for passive matrix
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* DSTN - for dual scan passive matrix
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* TFT - for active matrix
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*
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* bits 4 - 9 : for bus width
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* bits 10-17 : for AC Bias Pin Frequency
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* bit 18 : for output enable polarity
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* bit 19 : for pixel clock edge
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* bit 20 : for output pixel format when base is RGBT16
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*/
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#define LCD_CONN_TYPE(_x) ((_x) & 0x0f)
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#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f)
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#define LCD_TYPE_MASK 0xf
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#define LCD_TYPE_UNKNOWN 0
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#define LCD_TYPE_MONO_STN 1
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#define LCD_TYPE_MONO_DSTN 2
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#define LCD_TYPE_COLOR_STN 3
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#define LCD_TYPE_COLOR_DSTN 4
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#define LCD_TYPE_COLOR_TFT 5
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#define LCD_TYPE_SMART_PANEL 6
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#define LCD_TYPE_MAX 7
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#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN)
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#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN)
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#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN)
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#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN)
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#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
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#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT)
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#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
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#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
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#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
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#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
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#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
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#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
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#define LCD_BIAS_ACTIVE_HIGH (0 << 18)
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#define LCD_BIAS_ACTIVE_LOW (1 << 18)
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#define LCD_PCLK_EDGE_RISE (0 << 19)
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#define LCD_PCLK_EDGE_FALL (1 << 19)
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#define LCD_ALTERNATE_MAPPING (1 << 20)
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/*
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* This structure describes the machine which we are running on.
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* It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
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* of linux/drivers/video/pxafb.c
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*/
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struct pxafb_mode_info {
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u_long pixclock;
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u_short xres;
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u_short yres;
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u_char bpp;
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u_int cmap_greyscale:1,
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depth:8,
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transparency:1,
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unused:22;
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/* Parallel Mode Timing */
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u_char hsync_len;
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u_char left_margin;
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u_char right_margin;
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u_char vsync_len;
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u_char upper_margin;
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u_char lower_margin;
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u_char sync;
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/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
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* Note:
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* 1. all parameters in nanosecond (ns)
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* 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
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* in pxa27x and pxa3xx, initialize them to the same value or
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* the larger one will be used
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* 3. same to {rd,wr}_pulse_width
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*
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* 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
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* 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
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* 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
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*/
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unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
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unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
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unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
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unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
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unsigned cmd_inh_time; /* Command Inhibit time between two writes */
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unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
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};
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struct pxafb_mach_info {
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struct pxafb_mode_info *modes;
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unsigned int num_modes;
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unsigned int lcd_conn;
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unsigned long video_mem_size;
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u_int fixed_modes:1,
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cmap_inverse:1,
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cmap_static:1,
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acceleration_enabled:1,
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unused:28;
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/* The following should be defined in LCCR0
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* LCCR0_Act or LCCR0_Pas Active or Passive
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* LCCR0_Sngl or LCCR0_Dual Single/Dual panel
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* LCCR0_Mono or LCCR0_Color Mono/Color
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* LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
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* LCCR0_DMADel(Tcpu) (optional) DMA request delay
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*
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* The following should not be defined in LCCR0:
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* LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
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* LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
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*/
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u_int lccr0;
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/* The following should be defined in LCCR3
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* LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity
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* LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
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* LCCR3_Acb(X) AB Bias pin frequency
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* LCCR3_DPC (optional) Double Pixel Clock mode (untested)
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*
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* The following should not be defined in LCCR3
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* LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
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*/
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u_int lccr3;
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/* The following should be defined in LCCR4
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* LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
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*
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* All other bits in LCCR4 should be left alone.
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*/
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u_int lccr4;
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void (*pxafb_backlight_power)(int);
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void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
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void (*smart_update)(struct fb_info *);
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};
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void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
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unsigned long pxafb_get_hsync_time(struct device *dev);
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/* smartpanel related */
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#define SMART_CMD_A0 (0x1 << 8)
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#define SMART_CMD_READ_STATUS_REG (0x0 << 9)
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#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WRITE_COMMAND (0x1 << 9)
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#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
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#define SMART_CMD_NOOP (0x4 << 9)
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#define SMART_CMD_INTERRUPT (0x5 << 9)
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#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
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#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
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/* SMART_DELAY() is introduced for software controlled delay primitive which
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* can be inserted between command sequences, unused command 0x6 is used here
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* and delay ranges from 0ms ~ 255ms
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*/
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#define SMART_CMD_DELAY (0x6 << 9)
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#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff))
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
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extern int pxafb_smart_flush(struct fb_info *info);
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#else
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static inline int pxafb_smart_queue(struct fb_info *info,
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uint16_t *cmds, int n)
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{
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return 0;
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}
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static inline int pxafb_smart_flush(struct fb_info *info)
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{
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return 0;
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}
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#endif
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