188 lines
6.5 KiB
C
188 lines
6.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell OcteonTx2 CGX driver
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*
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* Copyright (C) 2018 Marvell.
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*
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*/
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#ifndef CGX_H
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#define CGX_H
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#include "mbox.h"
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#include "cgx_fw_if.h"
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#include "rpm.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_CGX 0xA059
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define CGX_ID_MASK 0x7
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#define MAX_LMAC_PER_CGX 4
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#define MAX_DMAC_ENTRIES_PER_CGX 32
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#define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */
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#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
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/* Registers */
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#define CGXX_CMRX_CFG 0x00
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#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)
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#define CMR_P2X_SEL_SHIFT 59ULL
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#define CMR_P2X_SEL_NIX0 1ULL
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#define CMR_P2X_SEL_NIX1 2ULL
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#define DATA_PKT_TX_EN BIT_ULL(53)
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#define DATA_PKT_RX_EN BIT_ULL(54)
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#define CGX_LMAC_TYPE_SHIFT 40
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#define CGX_LMAC_TYPE_MASK 0xF
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#define CGXX_CMRX_INT 0x040
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#define FW_CGX_INT BIT_ULL(1)
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#define CGXX_CMRX_INT_ENA_W1S 0x058
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#define CGXX_CMRX_RX_ID_MAP 0x060
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#define CGXX_CMRX_RX_STAT0 0x070
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#define CGXX_CMRX_RX_LMACS 0x128
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#define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
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#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
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#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
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#define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
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#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
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#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
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#define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
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#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
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#define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)
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#define CGXX_CMRX_RX_DMAC_CAM1 0x400
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#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
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#define CGXX_CMRX_TX_STAT0 0x700
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#define CGXX_SCRATCH0_REG 0x1050
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#define CGXX_SCRATCH1_REG 0x1058
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#define CGX_CONST 0x2000
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#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(23, 0)
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#define CGXX_SPUX_CONTROL1 0x10000
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#define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700
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#define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800
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#define CGXX_SPUX_RSFEC_CORR 0x10088
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#define CGXX_SPUX_RSFEC_UNCORR 0x10090
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#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
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#define CGXX_GMP_PCS_MRX_CTL 0x30000
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#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
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#define CGXX_SMUX_RX_FRM_CTL 0x20020
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#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
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#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)
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#define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028
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#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
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#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
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#define CGXX_SMUX_TX_CTL 0x20178
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#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
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#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
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#define CGXX_SMUX_SMAC 0x20108
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#define CGXX_SMUX_CBFC_CTL 0x20218
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#define CGXX_SMUX_CBFC_CTL_RX_EN BIT_ULL(0)
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#define CGXX_SMUX_CBFC_CTL_TX_EN BIT_ULL(1)
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#define CGXX_SMUX_CBFC_CTL_DRP_EN BIT_ULL(2)
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#define CGXX_SMUX_CBFC_CTL_BCK_EN BIT_ULL(3)
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#define CGX_PFC_CLASS_MASK GENMASK_ULL(47, 32)
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#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230
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#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248
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#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
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#define CGXX_CMR_RX_OVR_BP 0x130
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#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
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#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
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#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
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#define CGX_EVENT_REG CGXX_SCRATCH0_REG
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#define CGX_CMD_TIMEOUT 5000 /* msecs */
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#define DEFAULT_PAUSE_TIME 0x7FF
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#define CGX_LMAC_FWI 0
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enum cgx_nix_stat_type {
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NIX_STATS_RX,
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NIX_STATS_TX,
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};
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enum LMAC_TYPE {
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LMAC_MODE_SGMII = 0,
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LMAC_MODE_XAUI = 1,
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LMAC_MODE_RXAUI = 2,
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LMAC_MODE_10G_R = 3,
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LMAC_MODE_40G_R = 4,
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LMAC_MODE_QSGMII = 6,
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LMAC_MODE_25G_R = 7,
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LMAC_MODE_50G_R = 8,
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LMAC_MODE_100G_R = 9,
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LMAC_MODE_USXGMII = 10,
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LMAC_MODE_MAX,
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};
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struct cgx_link_event {
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struct cgx_link_user_info link_uinfo;
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u8 cgx_id;
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u8 lmac_id;
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};
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/**
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* struct cgx_event_cb
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* @notify_link_chg: callback for link change notification
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* @data: data passed to callback function
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*/
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struct cgx_event_cb {
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int (*notify_link_chg)(struct cgx_link_event *event, void *data);
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void *data;
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};
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extern struct pci_driver cgx_driver;
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int cgx_get_cgxcnt_max(void);
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int cgx_get_cgxid(void *cgxd);
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int cgx_get_lmac_cnt(void *cgxd);
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void *cgx_get_pdata(int cgx_id);
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int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
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int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
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int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
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int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
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int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
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int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
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int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
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u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
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int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
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int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
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int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
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void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
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void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
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int cgx_get_link_info(void *cgxd, int lmac_id,
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struct cgx_link_user_info *linfo);
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int cgx_lmac_linkup_start(void *cgxd);
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int cgx_get_fwdata_base(u64 *base);
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int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
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u8 *tx_pause, u8 *rx_pause);
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int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
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u8 tx_pause, u8 rx_pause);
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void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
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u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
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int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
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int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
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int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
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int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
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int cgx_id, int lmac_id);
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u64 cgx_features_get(void *cgxd);
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struct mac_ops *get_mac_ops(void *cgxd);
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int cgx_get_nr_lmacs(void *cgxd);
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u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
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unsigned long cgx_get_lmac_bmap(void *cgxd);
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void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
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u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
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int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
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u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
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u64 cgx_read_dmac_entry(void *cgxd, int index);
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int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
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u16 pfc_en);
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int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
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u8 *rx_pause);
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int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
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int pfvf_idx);
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#endif /* CGX_H */
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