326 lines
8.7 KiB
C
326 lines
8.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* S390 version
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* Copyright IBM Corp. 1999
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* Author(s): Hartmut Penner (hp@de.ibm.com),
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* Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/processor.h"
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* Copyright (C) 1994, Linus Torvalds
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*/
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#ifndef __ASM_S390_PROCESSOR_H
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#define __ASM_S390_PROCESSOR_H
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#include <linux/bits.h>
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#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
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#define CIF_FPU 3 /* restore FPU registers */
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#define CIF_ENABLED_WAIT 5 /* in enabled wait state */
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#define CIF_MCCK_GUEST 6 /* machine check happening in guest */
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#define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
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#define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
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#define _CIF_FPU BIT(CIF_FPU)
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#define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
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#define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
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#define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
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#define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
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#ifndef __ASSEMBLY__
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#include <linux/cpumask.h>
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <asm/cpu.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/setup.h>
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#include <asm/runtime_instr.h>
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#include <asm/fpu/types.h>
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#include <asm/fpu/internal.h>
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#include <asm/irqflags.h>
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typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
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static inline void set_cpu_flag(int flag)
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{
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S390_lowcore.cpu_flags |= (1UL << flag);
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}
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static inline void clear_cpu_flag(int flag)
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{
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S390_lowcore.cpu_flags &= ~(1UL << flag);
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}
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static inline int test_cpu_flag(int flag)
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{
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return !!(S390_lowcore.cpu_flags & (1UL << flag));
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}
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/*
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* Test CIF flag of another CPU. The caller needs to ensure that
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* CPU hotplug can not happen, e.g. by disabling preemption.
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*/
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static inline int test_cpu_flag_of(int flag, int cpu)
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{
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struct lowcore *lc = lowcore_ptr[cpu];
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return !!(lc->cpu_flags & (1UL << flag));
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}
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#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
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static inline void get_cpu_id(struct cpuid *ptr)
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{
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asm volatile("stidp %0" : "=Q" (*ptr));
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}
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void s390_adjust_jiffies(void);
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void s390_update_cpu_mhz(void);
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void cpu_detect_mhz_feature(void);
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extern const struct seq_operations cpuinfo_op;
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extern void execve_tail(void);
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extern void __bpon(void);
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unsigned long vdso_size(void);
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/*
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* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
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*/
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#define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
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_REGION3_SIZE : TASK_SIZE_MAX)
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#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
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(_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
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#define TASK_SIZE_MAX (-PAGE_SIZE)
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#define VDSO_BASE (STACK_TOP + PAGE_SIZE)
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#define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
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#define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
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#define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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/*
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* Thread structure
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*/
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struct thread_struct {
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unsigned int acrs[NUM_ACRS];
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unsigned long ksp; /* kernel stack pointer */
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unsigned long user_timer; /* task cputime in user space */
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unsigned long guest_timer; /* task cputime in kvm guest */
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unsigned long system_timer; /* task cputime in kernel space */
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unsigned long hardirq_timer; /* task cputime in hardirq context */
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unsigned long softirq_timer; /* task cputime in softirq context */
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const sys_call_ptr_t *sys_call_table; /* system call table address */
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unsigned long gmap_addr; /* address of last gmap fault. */
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unsigned int gmap_write_flag; /* gmap fault write indication */
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unsigned int gmap_int_code; /* int code of last gmap fault */
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unsigned int gmap_pfault; /* signal of a pending guest pfault */
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/* Per-thread information related to debugging */
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struct per_regs per_user; /* User specified PER registers */
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struct per_event per_event; /* Cause of the last PER trap */
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unsigned long per_flags; /* Flags to control debug behavior */
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unsigned int system_call; /* system call number in signal */
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unsigned long last_break; /* last breaking-event-address. */
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/* pfault_wait is used to block the process on a pfault event */
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unsigned long pfault_wait;
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struct list_head list;
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/* cpu runtime instrumentation */
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struct runtime_instr_cb *ri_cb;
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struct gs_cb *gs_cb; /* Current guarded storage cb */
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struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
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struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
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/*
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* Warning: 'fpu' is dynamically-sized. It *MUST* be at
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* the end.
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*/
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struct fpu fpu; /* FP and VX register save area */
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};
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/* Flag to disable transactions. */
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#define PER_FLAG_NO_TE 1UL
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/* Flag to enable random transaction aborts. */
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#define PER_FLAG_TE_ABORT_RAND 2UL
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/* Flag to specify random transaction abort mode:
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* - abort each transaction at a random instruction before TEND if set.
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* - abort random transactions at a random instruction if cleared.
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*/
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#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
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typedef struct thread_struct thread_struct;
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#define ARCH_MIN_TASKALIGN 8
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#define INIT_THREAD { \
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.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
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.fpu.regs = (void *) init_task.thread.fpu.fprs, \
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.last_break = 1, \
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}
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/*
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* Do necessary setup to start up a new thread.
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*/
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#define start_thread(regs, new_psw, new_stackp) do { \
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regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
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regs->psw.addr = new_psw; \
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regs->gprs[15] = new_stackp; \
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execve_tail(); \
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} while (0)
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#define start_thread31(regs, new_psw, new_stackp) do { \
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regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
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regs->psw.addr = new_psw; \
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regs->gprs[15] = new_stackp; \
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execve_tail(); \
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} while (0)
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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struct seq_file;
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struct pt_regs;
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void show_registers(struct pt_regs *regs);
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void show_cacheinfo(struct seq_file *m);
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/* Free guarded storage control block */
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void guarded_storage_release(struct task_struct *tsk);
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void gs_load_bc_cb(struct pt_regs *regs);
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unsigned long __get_wchan(struct task_struct *p);
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#define task_pt_regs(tsk) ((struct pt_regs *) \
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(task_stack_page(tsk) + THREAD_SIZE) - 1)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
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/* Has task runtime instrumentation enabled ? */
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#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
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/* avoid using global register due to gcc bug in versions < 8.4 */
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#define current_stack_pointer (__current_stack_pointer())
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static __always_inline unsigned long __current_stack_pointer(void)
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{
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unsigned long sp;
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asm volatile("lgr %0,15" : "=d" (sp));
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return sp;
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}
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static __always_inline unsigned short stap(void)
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{
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unsigned short cpu_address;
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asm volatile("stap %0" : "=Q" (cpu_address));
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return cpu_address;
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}
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#define cpu_relax() barrier()
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#define ECAG_CACHE_ATTRIBUTE 0
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#define ECAG_CPU_ATTRIBUTE 1
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static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
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{
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unsigned long val;
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asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
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return val;
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}
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static inline void psw_set_key(unsigned int key)
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{
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asm volatile("spka 0(%0)" : : "d" (key));
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}
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/*
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* Set PSW to specified value.
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*/
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static inline void __load_psw(psw_t psw)
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{
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asm volatile("lpswe %0" : : "Q" (psw) : "cc");
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}
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/*
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* Set PSW mask to specified value, while leaving the
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* PSW addr pointing to the next instruction.
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*/
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static __always_inline void __load_psw_mask(unsigned long mask)
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{
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unsigned long addr;
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psw_t psw;
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psw.mask = mask;
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asm volatile(
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" larl %0,1f\n"
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" stg %0,%1\n"
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" lpswe %2\n"
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"1:"
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: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
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}
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/*
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* Extract current PSW mask
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*/
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static inline unsigned long __extract_psw(void)
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{
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unsigned int reg1, reg2;
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asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
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return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
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}
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static inline void local_mcck_enable(void)
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{
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__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
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}
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static inline void local_mcck_disable(void)
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{
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__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
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}
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/*
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* Rewind PSW instruction address by specified number of bytes.
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*/
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static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
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{
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unsigned long mask;
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mask = (psw.mask & PSW_MASK_EA) ? -1UL :
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(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
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(1UL << 24) - 1;
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return (psw.addr - ilc) & mask;
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}
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/*
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* Function to drop a processor into disabled wait state
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*/
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static __always_inline void __noreturn disabled_wait(void)
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{
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psw_t psw;
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psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
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psw.addr = _THIS_IP_;
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__load_psw(psw);
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while (1);
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}
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#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
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extern int s390_isolate_bp(void);
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extern int s390_isolate_bp_guest(void);
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static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
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{
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return arch_irqs_disabled_flags(regs->psw.mask);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_S390_PROCESSOR_H */
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