131 lines
3.0 KiB
ArmAsm
131 lines
3.0 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/bug.h>
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#include <asm/regdef.h>
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#include <asm/loongarch.h>
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#include <asm/stackframe.h>
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#ifdef CONFIG_EFI_STUB
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#include "efi-header.S"
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__HEAD
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_head:
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.word MZ_MAGIC /* "MZ", MS-DOS header */
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.org 0x8
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.dword kernel_entry /* Kernel entry point */
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.dword _end - _text /* Kernel image effective size */
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.quad 0 /* Kernel image load offset from start of RAM */
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.org 0x3c /* 0x20 ~ 0x3b reserved */
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.long pe_header - _head /* Offset to the PE header */
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pe_header:
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__EFI_PE_HEADER
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SYM_DATA(kernel_asize, .long _end - _text);
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SYM_DATA(kernel_fsize, .long _edata - _text);
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SYM_DATA(kernel_offset, .long kernel_offset - _text);
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#endif
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__REF
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.align 12
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SYM_CODE_START(kernel_entry) # kernel entry point
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/* Config direct window and set PG */
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li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx
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csrwr t0, LOONGARCH_CSR_DMWIN0
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li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx
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csrwr t0, LOONGARCH_CSR_DMWIN1
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/* We might not get launched at the address the kernel is linked to,
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so we jump there. */
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la.abs t0, 0f
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jr t0
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0:
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/* Enable PG */
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li.w t0, 0xb0 # PLV=0, IE=0, PG=1
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csrwr t0, LOONGARCH_CSR_CRMD
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li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr t0, LOONGARCH_CSR_PRMD
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li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr t0, LOONGARCH_CSR_EUEN
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la.pcrel t0, __bss_start # clear .bss
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st.d zero, t0, 0
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la.pcrel t1, __bss_stop - LONGSIZE
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1:
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addi.d t0, t0, LONGSIZE
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st.d zero, t0, 0
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bne t0, t1, 1b
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la.pcrel t0, fw_arg0
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st.d a0, t0, 0 # firmware arguments
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la.pcrel t0, fw_arg1
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st.d a1, t0, 0
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la.pcrel t0, fw_arg2
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st.d a2, t0, 0
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/* KSave3 used for percpu base, initialized as 0 */
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csrwr zero, PERCPU_BASE_KS
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/* GPR21 used for percpu base (runtime), initialized as 0 */
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move u0, zero
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la.pcrel tp, init_thread_union
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/* Set the SP after an empty pt_regs. */
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PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
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PTR_ADD sp, sp, tp
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set_saved_sp sp, t0, t1
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bl start_kernel
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ASM_BUG()
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SYM_CODE_END(kernel_entry)
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#ifdef CONFIG_SMP
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/*
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* SMP slave cpus entry point. Board specific code for bootstrap calls this
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* function after setting up the stack and tp registers.
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*/
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SYM_CODE_START(smpboot_entry)
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li.d t0, CSR_DMW0_INIT # UC, PLV0
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csrwr t0, LOONGARCH_CSR_DMWIN0
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li.d t0, CSR_DMW1_INIT # CA, PLV0
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csrwr t0, LOONGARCH_CSR_DMWIN1
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la.abs t0, 0f
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jr t0
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0:
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/* Enable PG */
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li.w t0, 0xb0 # PLV=0, IE=0, PG=1
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csrwr t0, LOONGARCH_CSR_CRMD
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li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr t0, LOONGARCH_CSR_PRMD
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li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr t0, LOONGARCH_CSR_EUEN
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la.abs t0, cpuboot_data
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ld.d sp, t0, CPU_BOOT_STACK
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ld.d tp, t0, CPU_BOOT_TINFO
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bl start_secondary
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ASM_BUG()
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SYM_CODE_END(smpboot_entry)
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#endif /* CONFIG_SMP */
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SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)
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