311 lines
8.4 KiB
Plaintext
311 lines
8.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for Sunplus SP7021
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*
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* Copyright (C) 2021 Sunplus Technology Co.
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*/
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#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/reset/sunplus,sp7021-reset.h>
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#include <dt-bindings/pinctrl/sppctl-sp7021.h>
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#include <dt-bindings/gpio/gpio.h>
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#define XTAL 27000000
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/ {
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compatible = "sunplus,sp7021";
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model = "Sunplus SP7021";
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clocks {
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extclk: osc0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <XTAL>;
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clock-output-names = "extclk";
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};
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};
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soc@9c000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x9c000000 0x400000>;
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interrupt-parent = <&intc>;
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clkc: clock-controller@4 {
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compatible = "sunplus,sp7021-clkc";
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reg = <0x4 0x28>,
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<0x200 0x44>,
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<0x268 0x04>;
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clocks = <&extclk>;
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#clock-cells = <1>;
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};
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intc: interrupt-controller@780 {
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compatible = "sunplus,sp7021-intc";
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reg = <0x780 0x80>, <0xa80 0x80>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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otp: otp@af00 {
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compatible = "sunplus,sp7021-ocotp";
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reg = <0xaf00 0x34>, <0xaf80 0x58>;
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reg-names = "hb_gpio", "otprx";
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clocks = <&clkc CLK_OTPRX>;
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resets = <&rstc RST_OTPRX>;
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#address-cells = <1>;
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#size-cells = <1>;
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therm_calib: thermal-calibration@14 {
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reg = <0x14 0x3>;
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};
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disc_vol: disconnect-voltage@18 {
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reg = <0x18 0x2>;
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};
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mac_addr0: mac-address0@34 {
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reg = <0x34 0x6>;
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};
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mac_addr1: mac-address1@3a {
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reg = <0x3a 0x6>;
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};
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};
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pctl: pinctrl@100 {
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compatible = "sunplus,sp7021-pctl";
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reg = <0x100 0x100>,
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<0x300 0x100>,
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<0x32e4 0x1C>,
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<0x80 0x20>;
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reg-names = "moon2", "gpioxt", "first", "moon1";
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&clkc CLK_GPIO>;
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resets = <&rstc RST_GPIO>;
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emac_pins: pinmux-emac-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
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SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
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SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
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SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
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SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
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SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
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SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
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SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
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SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
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SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
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SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
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SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
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SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
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SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
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SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
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SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
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SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
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>;
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sunplus,zerofunc = <
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MUXF_L2SW_LED_FLASH0
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MUXF_L2SW_LED_FLASH1
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MUXF_L2SW_LED_ON0
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MUXF_L2SW_LED_ON1
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MUXF_DAISY_MODE
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>;
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};
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emmc_pins: pinmux-emmc-pins {
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function = "CARD0_EMMC";
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groups = "CARD0_EMMC";
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};
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leds_pins: pinmux-leds-pins {
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sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
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};
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sdcard_pins: pinmux-sdcard-pins {
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function = "SD_CARD";
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groups = "SD_CARD";
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sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
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};
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spi0_pins: pinmux-spi0-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
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SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
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SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
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SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
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SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
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>;
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};
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uart0_pins: pinmux-uart0-pins {
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function = "UA0";
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groups = "UA0";
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};
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uart1_pins: pinmux-uart1-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
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SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
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>;
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};
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uart2_pins: pinmux-uart2-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
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SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
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SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
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SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
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>;
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};
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uart4_pins: pinmux-uart4-pins {
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sunplus,pins = <
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SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
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SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
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SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
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SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
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>;
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};
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};
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rstc: reset@54 {
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compatible = "sunplus,sp7021-reset";
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reg = <0x54 0x28>;
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#reset-cells = <1>;
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};
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rtc: rtc@3a00 {
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compatible = "sunplus,sp7021-rtc";
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reg = <0x3a00 0x80>;
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reg-names = "rtc";
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clocks = <&clkc CLK_RTC>;
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resets = <&rstc RST_RTC>;
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interrupts = <163 IRQ_TYPE_EDGE_RISING>;
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};
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spi_controller0: spi@2d80 {
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compatible = "sunplus,sp7021-spi";
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reg = <0x2d80 0x80>, <0x2e00 0x80>;
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reg-names = "master", "slave";
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interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
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<146 IRQ_TYPE_LEVEL_HIGH>,
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<145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma_w", "master_risc", "slave_risc";
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clocks = <&clkc CLK_SPI_COMBO_0>;
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resets = <&rstc RST_SPI_COMBO_0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
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<&pctl 28 GPIO_ACTIVE_LOW>;
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};
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spi_controller1: spi@f480 {
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compatible = "sunplus,sp7021-spi";
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reg = <0xf480 0x80>, <0xf500 0x80>;
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reg-names = "master", "slave";
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interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
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<69 IRQ_TYPE_LEVEL_HIGH>,
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<68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma_w", "master_risc", "slave_risc";
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clocks = <&clkc CLK_SPI_COMBO_1>;
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resets = <&rstc RST_SPI_COMBO_1>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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spi_controller2: spi@f600 {
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compatible = "sunplus,sp7021-spi";
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reg = <0xf600 0x80>, <0xf680 0x80>;
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reg-names = "master", "slave";
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interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
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<72 IRQ_TYPE_LEVEL_HIGH>,
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<71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma_w", "master_risc", "slave_risc";
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clocks = <&clkc CLK_SPI_COMBO_2>;
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resets = <&rstc RST_SPI_COMBO_2>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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spi_controller3: spi@f780 {
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compatible = "sunplus,sp7021-spi";
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reg = <0xf780 0x80>, <0xf800 0x80>;
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reg-names = "master", "slave";
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interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
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<75 IRQ_TYPE_LEVEL_HIGH>,
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<74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma_w", "master_risc", "slave_risc";
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clocks = <&clkc CLK_SPI_COMBO_3>;
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resets = <&rstc RST_SPI_COMBO_3>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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uart0: serial@900 {
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compatible = "sunplus,sp7021-uart";
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reg = <0x900 0x80>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLK_UA0>;
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resets = <&rstc RST_UA0>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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uart1: serial@980 {
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compatible = "sunplus,sp7021-uart";
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reg = <0x980 0x80>;
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interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLK_UA1>;
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resets = <&rstc RST_UA1>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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uart2: serial@800 {
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compatible = "sunplus,sp7021-uart";
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reg = <0x800 0x80>;
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interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLK_UA2>;
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resets = <&rstc RST_UA2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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uart3: serial@880 {
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compatible = "sunplus,sp7021-uart";
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reg = <0x880 0x80>;
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interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLK_UA3>;
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resets = <&rstc RST_UA3>;
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status = "disabled";
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};
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uart4: serial@8780 {
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compatible = "sunplus,sp7021-uart";
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reg = <0x8780 0x80>;
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interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLK_UA4>;
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resets = <&rstc RST_UA4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins>;
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status = "disabled";
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&leds_pins>;
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system-led {
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label = "system-led";
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gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "heartbeat";
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};
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};
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};
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