881 lines
19 KiB
Plaintext
881 lines
19 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3066a-cru.h>
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#include <dt-bindings/power/rk3066-power.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3066a";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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operating-points =
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/* kHz uV */
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<1416000 1300000>,
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<1200000 1175000>,
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<1008000 1125000>,
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<816000 1125000>,
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<600000 1100000>,
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<504000 1100000>,
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<312000 1075000>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop0_out>, <&vop1_out>;
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x10000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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vop0: vop@1010c000 {
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compatible = "rockchip,rk3066-vop";
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reg = <0x1010c000 0x19c>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC0>,
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<&cru DCLK_LCDC0>,
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<&cru HCLK_LCDC0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3066_PD_VIO>;
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resets = <&cru SRST_LCDC0_AXI>,
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<&cru SRST_LCDC0_AHB>,
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<&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop0_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop0_out_hdmi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&hdmi_in_vop0>;
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};
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};
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};
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vop1: vop@1010e000 {
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compatible = "rockchip,rk3066-vop";
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reg = <0x1010e000 0x19c>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC1>,
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<&cru DCLK_LCDC1>,
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<&cru HCLK_LCDC1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3066_PD_VIO>;
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resets = <&cru SRST_LCDC1_AXI>,
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<&cru SRST_LCDC1_AHB>,
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<&cru SRST_LCDC1_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop1_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop1_out_hdmi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&hdmi_in_vop1>;
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};
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};
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};
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hdmi: hdmi@10116000 {
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compatible = "rockchip,rk3066-hdmi";
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reg = <0x10116000 0x2000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HDMI>;
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clock-names = "hclk";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
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power-domains = <&power RK3066_PD_VIO>;
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rockchip,grf = <&grf>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vop0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop0_out_hdmi>;
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};
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hdmi_in_vop1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vop1_out_hdmi>;
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};
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};
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hdmi_out: port@1 {
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reg = <1>;
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};
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};
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};
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i2s0: i2s@10118000 {
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compatible = "rockchip,rk3066-i2s";
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reg = <0x10118000 0x2000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
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clock-names = "i2s_clk", "i2s_hclk";
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dmas = <&dmac1_s 4>, <&dmac1_s 5>;
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dma-names = "tx", "rx";
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rockchip,playback-channels = <8>;
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rockchip,capture-channels = <2>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s1: i2s@1011a000 {
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compatible = "rockchip,rk3066-i2s";
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reg = <0x1011a000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
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clock-names = "i2s_clk", "i2s_hclk";
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dmas = <&dmac1_s 6>, <&dmac1_s 7>;
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dma-names = "tx", "rx";
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rockchip,playback-channels = <2>;
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rockchip,capture-channels = <2>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s2: i2s@1011c000 {
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compatible = "rockchip,rk3066-i2s";
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reg = <0x1011c000 0x2000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s2_bus>;
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clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
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clock-names = "i2s_clk", "i2s_hclk";
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dmas = <&dmac1_s 9>, <&dmac1_s 10>;
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dma-names = "tx", "rx";
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rockchip,playback-channels = <2>;
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rockchip,capture-channels = <2>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3066a-cru";
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reg = <0x20000000 0x1000>;
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clocks = <&xin24m>;
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clock-names = "xin24m";
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
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<&cru ACLK_CPU>, <&cru HCLK_CPU>,
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<&cru PCLK_CPU>, <&cru ACLK_PERI>,
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<&cru HCLK_PERI>, <&cru PCLK_PERI>;
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assigned-clock-rates = <400000000>, <594000000>,
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<300000000>, <150000000>,
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<75000000>, <300000000>,
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<150000000>, <75000000>;
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};
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timer2: timer@2000e000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2000e000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
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clock-names = "timer", "pclk";
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};
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efuse: efuse@20010000 {
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compatible = "rockchip,rk3066a-efuse";
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reg = <0x20010000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_EFUSE>;
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clock-names = "pclk_efuse";
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cpu_leakage: cpu_leakage@17 {
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reg = <0x17 0x1>;
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};
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};
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timer0: timer@20038000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x20038000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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timer1: timer@2003a000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2003a000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
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clock-names = "timer", "pclk";
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};
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tsadc: tsadc@20060000 {
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compatible = "rockchip,rk3066-tsadc";
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reg = <0x20060000 0x100>;
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clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
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clock-names = "saradc", "apb_pclk";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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resets = <&cru SRST_TSADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3066a-pinctrl";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio@20034000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20034000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@20084000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@2000a000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO6>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_default: pcfg-pull-default {
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bias-pull-pin-default;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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emac {
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emac_xfer: emac-xfer {
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|
|
rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
|
||
|
|
<1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
|
||
|
|
<1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
|
||
|
|
<1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
|
||
|
|
<1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
|
||
|
|
<1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
|
||
|
|
<1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
|
||
|
|
<1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
|
||
|
|
};
|
||
|
|
|
||
|
|
emac_mdio: emac-mdio {
|
||
|
|
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
|
||
|
|
<1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
emmc {
|
||
|
|
emmc_clk: emmc-clk {
|
||
|
|
rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
emmc_cmd: emmc-cmd {
|
||
|
|
rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
emmc_rst: emmc-rst {
|
||
|
|
rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The data pins are shared between nandc and emmc and
|
||
|
|
* not accessible through pinctrl. Also they should've
|
||
|
|
* been already set correctly by firmware, as
|
||
|
|
* flash/emmc is the boot-device.
|
||
|
|
*/
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmi {
|
||
|
|
hdmi_hpd: hdmi-hpd {
|
||
|
|
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmii2c_xfer: hdmii2c-xfer {
|
||
|
|
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
|
||
|
|
<0 RK_PA2 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c0 {
|
||
|
|
i2c0_xfer: i2c0-xfer {
|
||
|
|
rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
|
||
|
|
<2 RK_PD5 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1 {
|
||
|
|
i2c1_xfer: i2c1-xfer {
|
||
|
|
rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
|
||
|
|
<2 RK_PD7 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2 {
|
||
|
|
i2c2_xfer: i2c2-xfer {
|
||
|
|
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
|
||
|
|
<3 RK_PA1 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3 {
|
||
|
|
i2c3_xfer: i2c3-xfer {
|
||
|
|
rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
|
||
|
|
<3 RK_PA3 2 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4 {
|
||
|
|
i2c4_xfer: i2c4-xfer {
|
||
|
|
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
|
||
|
|
<3 RK_PA5 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm0 {
|
||
|
|
pwm0_out: pwm0-out {
|
||
|
|
rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm1 {
|
||
|
|
pwm1_out: pwm1-out {
|
||
|
|
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm2 {
|
||
|
|
pwm2_out: pwm2-out {
|
||
|
|
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwm3 {
|
||
|
|
pwm3_out: pwm3-out {
|
||
|
|
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi0 {
|
||
|
|
spi0_clk: spi0-clk {
|
||
|
|
rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi0_cs0: spi0-cs0 {
|
||
|
|
rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi0_tx: spi0-tx {
|
||
|
|
rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi0_rx: spi0-rx {
|
||
|
|
rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi0_cs1: spi0-cs1 {
|
||
|
|
rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1 {
|
||
|
|
spi1_clk: spi1-clk {
|
||
|
|
rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi1_cs0: spi1-cs0 {
|
||
|
|
rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi1_rx: spi1-rx {
|
||
|
|
rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi1_tx: spi1-tx {
|
||
|
|
rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
spi1_cs1: spi1-cs1 {
|
||
|
|
rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0 {
|
||
|
|
uart0_xfer: uart0-xfer {
|
||
|
|
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
|
||
|
|
<1 RK_PA1 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0_cts: uart0-cts {
|
||
|
|
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0_rts: uart0-rts {
|
||
|
|
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1 {
|
||
|
|
uart1_xfer: uart1-xfer {
|
||
|
|
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
|
||
|
|
<1 RK_PA5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1_cts: uart1-cts {
|
||
|
|
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1_rts: uart1-rts {
|
||
|
|
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
uart2 {
|
||
|
|
uart2_xfer: uart2-xfer {
|
||
|
|
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
|
||
|
|
<1 RK_PB1 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
/* no rts / cts for uart2 */
|
||
|
|
};
|
||
|
|
|
||
|
|
uart3 {
|
||
|
|
uart3_xfer: uart3-xfer {
|
||
|
|
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PD4 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart3_cts: uart3-cts {
|
||
|
|
rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart3_rts: uart3-rts {
|
||
|
|
rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0 {
|
||
|
|
sd0_clk: sd0-clk {
|
||
|
|
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0_cmd: sd0-cmd {
|
||
|
|
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0_cd: sd0-cd {
|
||
|
|
rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0_wp: sd0-wp {
|
||
|
|
rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0_bus1: sd0-bus-width1 {
|
||
|
|
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd0_bus4: sd0-bus-width4 {
|
||
|
|
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PB3 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PB4 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PB5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1 {
|
||
|
|
sd1_clk: sd1-clk {
|
||
|
|
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1_cmd: sd1-cmd {
|
||
|
|
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1_cd: sd1-cd {
|
||
|
|
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1_wp: sd1-wp {
|
||
|
|
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1_bus1: sd1-bus-width1 {
|
||
|
|
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sd1_bus4: sd1-bus-width4 {
|
||
|
|
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PC2 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PC3 1 &pcfg_pull_default>,
|
||
|
|
<3 RK_PC4 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s0 {
|
||
|
|
i2s0_bus: i2s0-bus {
|
||
|
|
rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB0 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB1 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB2 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB3 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB4 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB5 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB6 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PB7 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s1 {
|
||
|
|
i2s1_bus: i2s1-bus {
|
||
|
|
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PC1 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PC2 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PC3 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PC4 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PC5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s2 {
|
||
|
|
i2s2_bus: i2s2-bus {
|
||
|
|
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PD1 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PD2 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PD3 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PD4 1 &pcfg_pull_default>,
|
||
|
|
<0 RK_PD5 1 &pcfg_pull_default>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&gpu {
|
||
|
|
compatible = "rockchip,rk3066-mali", "arm,mali-400";
|
||
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "gp",
|
||
|
|
"gpmmu",
|
||
|
|
"pp0",
|
||
|
|
"ppmmu0",
|
||
|
|
"pp1",
|
||
|
|
"ppmmu1",
|
||
|
|
"pp2",
|
||
|
|
"ppmmu2",
|
||
|
|
"pp3",
|
||
|
|
"ppmmu3";
|
||
|
|
power-domains = <&power RK3066_PD_GPU>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&grf {
|
||
|
|
compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
|
||
|
|
|
||
|
|
usbphy: usbphy {
|
||
|
|
compatible = "rockchip,rk3066a-usb-phy";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
usbphy0: usb-phy@17c {
|
||
|
|
reg = <0x17c>;
|
||
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
||
|
|
clock-names = "phyclk";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usbphy1: usb-phy@188 {
|
||
|
|
reg = <0x188>;
|
||
|
|
clocks = <&cru SCLK_OTGPHY1>;
|
||
|
|
clock-names = "phyclk";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c0 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&i2c0_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&i2c1_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c2 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&i2c2_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c3 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&i2c3_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c4 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&i2c4_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&mmc0 {
|
||
|
|
clock-frequency = <50000000>;
|
||
|
|
dmas = <&dmac2 1>;
|
||
|
|
dma-names = "rx-tx";
|
||
|
|
max-frequency = <50000000>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&mmc1 {
|
||
|
|
dmas = <&dmac2 3>;
|
||
|
|
dma-names = "rx-tx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&emmc {
|
||
|
|
dmas = <&dmac2 4>;
|
||
|
|
dma-names = "rx-tx";
|
||
|
|
};
|
||
|
|
|
||
|
|
&pmu {
|
||
|
|
power: power-controller {
|
||
|
|
compatible = "rockchip,rk3066-power-controller";
|
||
|
|
#power-domain-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
power-domain@RK3066_PD_VIO {
|
||
|
|
reg = <RK3066_PD_VIO>;
|
||
|
|
clocks = <&cru ACLK_LCDC0>,
|
||
|
|
<&cru ACLK_LCDC1>,
|
||
|
|
<&cru DCLK_LCDC0>,
|
||
|
|
<&cru DCLK_LCDC1>,
|
||
|
|
<&cru HCLK_LCDC0>,
|
||
|
|
<&cru HCLK_LCDC1>,
|
||
|
|
<&cru SCLK_CIF1>,
|
||
|
|
<&cru ACLK_CIF1>,
|
||
|
|
<&cru HCLK_CIF1>,
|
||
|
|
<&cru SCLK_CIF0>,
|
||
|
|
<&cru ACLK_CIF0>,
|
||
|
|
<&cru HCLK_CIF0>,
|
||
|
|
<&cru HCLK_HDMI>,
|
||
|
|
<&cru ACLK_IPP>,
|
||
|
|
<&cru HCLK_IPP>,
|
||
|
|
<&cru ACLK_RGA>,
|
||
|
|
<&cru HCLK_RGA>;
|
||
|
|
pm_qos = <&qos_lcdc0>,
|
||
|
|
<&qos_lcdc1>,
|
||
|
|
<&qos_cif0>,
|
||
|
|
<&qos_cif1>,
|
||
|
|
<&qos_ipp>,
|
||
|
|
<&qos_rga>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
power-domain@RK3066_PD_VIDEO {
|
||
|
|
reg = <RK3066_PD_VIDEO>;
|
||
|
|
clocks = <&cru ACLK_VDPU>,
|
||
|
|
<&cru ACLK_VEPU>,
|
||
|
|
<&cru HCLK_VDPU>,
|
||
|
|
<&cru HCLK_VEPU>;
|
||
|
|
pm_qos = <&qos_vpu>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
power-domain@RK3066_PD_GPU {
|
||
|
|
reg = <RK3066_PD_GPU>;
|
||
|
|
clocks = <&cru ACLK_GPU>;
|
||
|
|
pm_qos = <&qos_gpu>;
|
||
|
|
#power-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm0 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pwm0_out>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pwm1_out>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm2 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pwm2_out>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&pwm3 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&pwm3_out>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&spi0 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&spi1 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart0 {
|
||
|
|
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||
|
|
dmas = <&dmac1_s 0>, <&dmac1_s 1>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&uart0_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart1 {
|
||
|
|
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||
|
|
dmas = <&dmac1_s 2>, <&dmac1_s 3>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&uart1_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart2 {
|
||
|
|
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||
|
|
dmas = <&dmac2 6>, <&dmac2 7>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&uart2_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&uart3 {
|
||
|
|
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
|
||
|
|
dmas = <&dmac2 8>, <&dmac2 9>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&uart3_xfer>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&vpu {
|
||
|
|
power-domains = <&power RK3066_PD_VIDEO>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&wdt {
|
||
|
|
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
|
||
|
|
};
|
||
|
|
|
||
|
|
&emac {
|
||
|
|
compatible = "rockchip,rk3066-emac";
|
||
|
|
};
|