69 lines
1.3 KiB
Plaintext
69 lines
1.3 KiB
Plaintext
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Intel KIXRP435 Control Plane
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* processor reference design.
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*/
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/dts-v1/;
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#include "intel-ixp43x.dtsi"
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#include "intel-ixp4xx-reference-design.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Intel KIXRP435 Reference Design";
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compatible = "intel,kixrp435", "intel,ixp43x";
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#address-cells = <1>;
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#size-cells = <1>;
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 16 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x1000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x0fe0000 */
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fis-index-block = <0x7f>;
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};
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};
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};
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/* CHECKME: ethernet set-up taken from Gateworks Cambria */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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};
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};
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ethernet@c800c000 {
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status = "ok";
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queue-rx = <&qmgr 2>;
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queue-txready = <&qmgr 19>;
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phy-mode = "rgmii";
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phy-handle = <&phy2>;
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intel,npe-handle = <&npe 0>;
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};
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};
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};
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