749 lines
20 KiB
Plaintext
749 lines
20 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright 2018-2022 Toradex
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*/
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#include "imx6ull.dtsi"
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/ {
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/* Ethernet aliases to ensure correct MAC addresses */
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aliases {
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ethernet0 = &fec2;
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ethernet1 = &fec1;
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_bl_on>;
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power-supply = <®_3v3>;
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pwms = <&pwm4 0 5000000 1>;
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status = "okay";
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
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wakeup {
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debounce-interval = <10>;
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
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label = "Wake-Up";
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linux,code = <KEY_WAKEUP>;
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wakeup-source;
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};
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};
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panel_dpi: panel-dpi {
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compatible = "edt,et057090dhu";
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backlight = <&backlight>;
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power-supply = <®_3v3>;
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status = "okay";
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port {
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lcd_panel_in: endpoint {
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remote-endpoint = <&lcdif_out>;
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};
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};
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};
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reg_module_3v3: regulator-module-3v3 {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-name = "+V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_module_3v3_avdd: regulator-module-3v3-avdd {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-name = "+V3.3_AVDD_AUDIO";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_sd1_vqmmc: regulator-sd1-vqmmc {
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compatible = "regulator-gpio";
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gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_snvs_reg_sd>;
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regulator-always-on;
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regulator-name = "+V3.3_1.8_SD";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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states = <1800000 0x1 3300000 0x0>;
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vin-supply = <®_module_3v3>;
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};
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reg_eth_phy: regulator-eth-phy {
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compatible = "regulator-fixed-clock";
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "+V3.3_ETH";
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regulator-type = "voltage";
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vin-supply = <®_module_3v3>;
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clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
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startup-delay-us = <150000>;
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};
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};
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&adc1 {
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vref-supply = <®_module_3v3_avdd>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc1>;
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "disabled";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "disabled";
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};
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/* Colibri SPI */
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&ecspi1 {
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cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
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};
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/* Ethernet */
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&fec2 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_enet2>;
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pinctrl-1 = <&pinctrl_enet2_sleep>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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phy-supply = <®_eth_phy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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max-speed = <100>;
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reg = <2>;
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};
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};
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};
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/* NAND */
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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fsl,use-minimum-ecc;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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status = "okay";
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};
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/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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/* Atmel maxtouch controller */
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atmel_mxt_ts: touchscreen@4a {
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compatible = "atmel,maxtouch";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
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reg = <0x4a>;
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interrupt-parent = <&gpio5>;
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interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
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reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
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status = "disabled";
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};
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};
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/*
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* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
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* touch screen controller
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*/
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&i2c2 {
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/* Use low frequency to compensate for the high pull-up values. */
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clock-frequency = <40000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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ad7879_ts: touchscreen@2c {
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compatible = "adi,ad7879-1";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
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reg = <0x2c>;
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interrupt-parent = <&gpio5>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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touchscreen-max-pressure = <4096>;
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adi,resistance-plate-x = <120>;
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adi,first-conversion-delay = /bits/ 8 <3>;
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adi,acquisition-time = /bits/ 8 <1>;
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adi,median-filter-size = /bits/ 8 <2>;
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adi,averaging = /bits/ 8 <1>;
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adi,conversion-interval = /bits/ 8 <255>;
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};
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};
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&lcdif {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat
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&pinctrl_lcdif_ctrl>;
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port {
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lcdif_out: endpoint {
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remote-endpoint = <&lcd_panel_in>;
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};
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};
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};
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/* PWM <A> */
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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};
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/* PWM <B> */
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&pwm5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm5>;
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};
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/* PWM <C> */
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&pwm6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm6>;
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};
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/* PWM <D> */
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&pwm7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm7>;
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};
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&sdma {
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status = "okay";
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};
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&snvs_pwrkey {
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status = "disabled";
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};
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/* Colibri UART_A */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
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uart-has-rtscts;
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fsl,dte-mode;
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};
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/* Colibri UART_B */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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fsl,dte-mode;
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};
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/* Colibri UART_C */
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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fsl,dte-mode;
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};
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/* Colibri USBC */
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&usbotg1 {
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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};
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/* Colibri USBH */
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&usbotg2 {
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dr_mode = "host";
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};
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/* Colibri MMC/SD */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
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pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
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assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
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assigned-clock-rates = <0>, <198000000>;
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bus-width = <4>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
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disable-wp;
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keep-power-in-suspend;
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no-1-8-v;
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vqmmc-supply = <®_sd1_vqmmc>;
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wakeup-source;
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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};
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&iomuxc {
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pinctrl_adc1: adc1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
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MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
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MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
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>;
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};
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pinctrl_atmel_adap: atmeladapgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
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MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
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>;
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};
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pinctrl_atmel_conn: atmelconngrp {
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fsl,pins = <
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
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>;
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};
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pinctrl_can_int: canintgrp {
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fsl,pins = <
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MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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|
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_enet2_sleep: enet2-sleepgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
|
||
|
|
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
|
||
|
|
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
|
||
|
|
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
|
||
|
|
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
|
||
|
|
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
|
||
|
|
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
||
|
|
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
|
||
|
|
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
|
||
|
|
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi1_cs: ecspi1csgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ecspi1: ecspi1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
|
||
|
|
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
|
||
|
|
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan1: flexcan1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
|
||
|
|
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_flexcan2: flexcan2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
|
||
|
|
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio_bl_on: gpioblongrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio1: gpio1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
|
||
|
|
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
|
||
|
|
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
|
||
|
|
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
|
||
|
|
MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
|
||
|
|
MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
|
||
|
|
MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
|
||
|
|
MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio2: gpio2grp { /* Camera */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
|
||
|
|
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
|
||
|
|
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
|
||
|
|
MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
|
||
|
|
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio3: gpio3grp { /* CAN2 */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
|
||
|
|
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio4: gpio4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio6: gpio6grp { /* Wifi pins */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
|
||
|
|
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
|
||
|
|
MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
|
||
|
|
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
|
||
|
|
MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
|
||
|
|
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
|
||
|
|
MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpio7: gpio7grp { /* CAN1 */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
|
||
|
|
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* With an eMMC instead of a raw NAND device the following pins
|
||
|
|
* are available at SODIMM pins.
|
||
|
|
*/
|
||
|
|
pinctrl_gpmi_gpio: gpmigpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
|
||
|
|
MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
|
||
|
|
MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */
|
||
|
|
MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
|
||
|
|
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
|
||
|
|
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
|
||
|
|
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
|
||
|
|
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
|
||
|
|
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
|
||
|
|
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
|
||
|
|
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
|
||
|
|
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1_gpio: i2c1-gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
|
||
|
|
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
|
||
|
|
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2_gpio: i2c2-gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
|
||
|
|
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_lcdif_dat: lcdifdatgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
|
||
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
|
||
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
|
||
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
|
||
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
|
||
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
|
||
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
|
||
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
|
||
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
|
||
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
|
||
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
|
||
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
|
||
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
|
||
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
|
||
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
|
||
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
|
||
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
|
||
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
|
||
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
|
||
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
|
||
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm4: pwm4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm5: pwm5grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm6: pwm6grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_pwm7: pwm7grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
|
||
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
|
||
|
|
MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
|
||
|
|
MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
|
||
|
|
MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
|
||
|
|
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
|
||
|
|
MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
|
||
|
|
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
|
||
|
|
MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
|
||
|
|
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
pinctrl_uart5: uart5grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
|
||
|
|
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usbh_reg: usbhreggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
|
||
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
|
||
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
|
||
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
|
||
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
|
||
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
||
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
||
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
||
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
||
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
||
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
||
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
||
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
||
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
||
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
||
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
|
||
|
|
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
|
||
|
|
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
|
||
|
|
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
|
||
|
|
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
|
||
|
|
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
|
||
|
|
|
||
|
|
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2emmc: usdhc2emmcgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
|
||
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
|
||
|
|
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&iomuxc_snvs {
|
||
|
|
pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_gpio1: snvsgpio1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
|
||
|
|
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_reg_sd: snvsregsdgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_usbc_det: snvsusbcdetgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_snvs_wifi_pdn: snvswifipdngrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|