183 lines
6.6 KiB
ReStructuredText
183 lines
6.6 KiB
ReStructuredText
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============================
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Core Driver Infrastructure
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============================
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GPU Hardware Structure
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======================
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Each ASIC is a collection of hardware blocks. We refer to them as
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"IPs" (Intellectual Property blocks). Each IP encapsulates certain
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functionality. IPs are versioned and can also be mixed and matched.
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E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.
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The driver is arranged by IPs. There are driver components to handle
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the initialization and operation of each IP. There are also a bunch
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of smaller IPs that don't really need much if any driver interaction.
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Those end up getting lumped into the common stuff in the soc files.
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The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects of
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the SoC itself rather than specific IPs. E.g., things like GPU resets
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and register access functions are SoC dependent.
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An APU contains more than just CPU and GPU, it also contains all of
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the platform stuff (audio, usb, gpio, etc.). Also, a lot of
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components are shared between the CPU, platform, and the GPU (e.g.,
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SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have
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their interface to interact with those common components. For things
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like S0i3 there is a ton of coordination required across all the
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components, but that is probably a bit beyond the scope of this
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section.
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With respect to the GPU, we have the following major IPs:
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GMC (Graphics Memory Controller)
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This was a dedicated IP on older pre-vega chips, but has since
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become somewhat decentralized on vega and newer chips. They now
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have dedicated memory hubs for specific IPs or groups of IPs. We
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still treat it as a single component in the driver however since
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the programming model is still pretty similar. This is how the
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different IPs on the GPU get the memory (VRAM or system memory).
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It also provides the support for per process GPU virtual address
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spaces.
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IH (Interrupt Handler)
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This is the interrupt controller on the GPU. All of the IPs feed
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their interrupts into this IP and it aggregates them into a set of
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ring buffers that the driver can parse to handle interrupts from
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different IPs.
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PSP (Platform Security Processor)
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This handles security policy for the SoC and executes trusted
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applications, and validates and loads firmwares for other blocks.
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SMU (System Management Unit)
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This is the power management microcontroller. It manages the entire
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SoC. The driver interacts with it to control power management
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features like clocks, voltages, power rails, etc.
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DCN (Display Controller Next)
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This is the display controller. It handles the display hardware.
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It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
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SDMA (System DMA)
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This is a multi-purpose DMA engine. The kernel driver uses it for
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various things including paging and GPU page table updates. It's also
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exposed to userspace for use by user mode drivers (OpenGL, Vulkan,
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etc.)
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GC (Graphics and Compute)
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This is the graphics and compute engine, i.e., the block that
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encompasses the 3D pipeline and and shader blocks. This is by far the
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largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
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addition to that, it also contains the CP microcontrollers (ME, PFP,
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CE, MEC) and the RLC microcontroller. It's exposed to userspace for
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user mode drivers (OpenGL, Vulkan, OpenCL, etc.)
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VCN (Video Core Next)
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This is the multi-media engine. It handles video and image encode and
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decode. It's exposed to userspace for user mode drivers (VA-API,
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OpenMAX, etc.)
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Graphics and Compute Microcontrollers
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-------------------------------------
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CP (Command Processor)
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The name for the hardware block that encompasses the front end of the
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GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
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(PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
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provides the driver interface to interact with the GFX/Compute engine.
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MEC (MicroEngine Compute)
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This is the microcontroller that controls the compute queues on the
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GFX/compute engine.
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MES (MicroEngine Scheduler)
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This is a new engine for managing queues. This is currently unused.
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RLC (RunList Controller)
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This is another microcontroller in the GFX/Compute engine. It handles
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power management related functionality within the GFX/Compute engine.
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The name is a vestige of old hardware where it was originally added
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and doesn't really have much relation to what the engine does now.
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Driver Structure
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================
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In general, the driver has a list of all of the IPs on a particular
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SoC and for things like init/fini/suspend/resume, more or less just
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walks the list and handles each IP.
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Some useful constructs:
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KIQ (Kernel Interface Queue)
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This is a control queue used by the kernel driver to manage other gfx
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and compute queues on the GFX/compute engine. You can use it to
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map/unmap additional queues, etc.
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IB (Indirect Buffer)
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A command buffer for a particular engine. Rather than writing
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commands directly to the queue, you can write the commands into a
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piece of memory and then put a pointer to the memory into the queue.
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The hardware will then follow the pointer and execute the commands in
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the memory, then returning to the rest of the commands in the ring.
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.. _amdgpu_memory_domains:
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Memory Domains
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==============
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.. kernel-doc:: include/uapi/drm/amdgpu_drm.h
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:doc: memory domains
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Buffer Objects
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==============
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
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:doc: amdgpu_object
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
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:internal:
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PRIME Buffer Sharing
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====================
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
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:doc: PRIME Buffer Sharing
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
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:internal:
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MMU Notifier
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============
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
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:doc: MMU Notifier
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
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:internal:
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AMDGPU Virtual Memory
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=====================
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
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:doc: GPUVM
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
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:internal:
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Interrupt Handling
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==================
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
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:doc: Interrupt Handling
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.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
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:internal:
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IP Blocks
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=========
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.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
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:doc: IP Blocks
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.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
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:identifiers: amd_ip_block_type amd_ip_funcs
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