89 lines
2.0 KiB
YAML
89 lines
2.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier USB2 PHY
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description: |
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This describes the devicetree bindings for PHY interface built into
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USB2 controller implemented on Socionext UniPhier SoCs.
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Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
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controller doesn't include its own High-Speed PHY. This needs to specify
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USB2 PHY instead of USB3 HS-PHY.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro4-usb2-phy
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- socionext,uniphier-ld11-usb2-phy
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^phy@[0-9]+$":
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type: object
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additionalProperties: false
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properties:
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reg:
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minimum: 0
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maximum: 3
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description:
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The ID number for the PHY
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"#phy-cells":
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const: 0
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vbus-supply:
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description: A phandle to the regulator for USB VBUS, only for USB host
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required:
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- reg
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- "#phy-cells"
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required:
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- compatible
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- "#address-cells"
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- "#size-cells"
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additionalProperties: false
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examples:
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- |
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// The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.
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soc-glue@5f800000 {
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compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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usb-controller {
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compatible = "socionext,uniphier-ld11-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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usb_phy0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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usb_phy1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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usb_phy2: phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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};
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};
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};
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