120 lines
2.8 KiB
YAML
120 lines
2.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung SoC series PCIe Host Controller
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maintainers:
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- Marek Szyprowski <m.szyprowski@samsung.com>
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- Jaehoon Chung <jh80.chung@samsung.com>
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description: |+
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Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: samsung,exynos5433-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: External Local Bus interface (ELBI) registers.
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- description: PCIe configuration space region.
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reg-names:
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items:
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- const: dbi
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- const: elbi
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- const: config
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: PCIe bridge clock
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- description: PCIe bus clock
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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phys:
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maxItems: 1
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vdd10-supply:
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description:
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Phandle to a regulator that provides 1.0V power to the PCIe block.
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vdd18-supply:
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description:
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Phandle to a regulator that provides 1.8V power to the PCIe block.
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num-lanes:
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const: 1
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num-viewport:
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const: 3
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required:
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- reg
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- reg-names
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- interrupts
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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- ranges
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- bus-range
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- device_type
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- num-lanes
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- num-viewport
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- clocks
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- clock-names
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- phys
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- vdd10-supply
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- vdd18-supply
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/exynos5433.h>
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pcie: pcie@15700000 {
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compatible = "samsung,exynos5433-pcie";
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reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
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reg-names = "dbi", "elbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
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clock-names = "pcie", "pcie_bus";
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phys = <&pcie_phy>;
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pinctrl-0 = <&pcie_bus &pcie_wlanen>;
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pinctrl-names = "default";
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num-lanes = <1>;
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num-viewport = <3>;
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
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<0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
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vdd10-supply = <&ldo6_reg>;
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vdd18-supply = <&ldo7_reg>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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