130 lines
3.2 KiB
YAML
130 lines
3.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments GPMC NAND Flash controller.
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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- Roger Quadros <rogerq@kernel.org>
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description:
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GPMC NAND controller/Flash is represented as a child of the
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GPMC controller node.
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properties:
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compatible:
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items:
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- enum:
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- ti,am64-nand
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- ti,omap2-nand
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Interrupt for fifoevent
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- description: Interrupt for termcount
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"#address-cells": true
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"#size-cells": true
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ti,nand-ecc-opt:
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description: Desired ECC algorithm
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$ref: /schemas/types.yaml#/definitions/string
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enum: [sw, ham1, bch4, bch8, bch16]
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ti,nand-xfer-type:
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description: Data transfer method between controller and chip.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
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default: prefetch-polled
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ti,elm-id:
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description:
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phandle to the ELM (Error Location Module).
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$ref: /schemas/types.yaml#/definitions/phandle
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nand-bus-width:
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description:
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Bus width to the NAND chip
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16]
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default: 8
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rb-gpios:
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description:
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GPIO connection to R/B signal from NAND chip
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maxItems: 1
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patternProperties:
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"@[0-9a-f]+$":
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$ref: "/schemas/mtd/partitions/partition.yaml"
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allOf:
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- $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
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required:
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- compatible
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- reg
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- ti,nand-ecc-opt
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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gpmc: memory-controller@50000000 {
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compatible = "ti,am3352-gpmc";
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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clocks = <&l3s_gclk>;
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clock-names = "fck";
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reg = <0x50000000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <7>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* device IO registers */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-xfer-type = "prefetch-dma";
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ti,nand-ecc-opt = "bch16";
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ti,elm-id = <&elm>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* NAND generic properties */
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nand-bus-width = <8>;
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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/* GPMC properties*/
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gpmc,device-width = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x00040000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00040000 0x00040000>;
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};
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};
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};
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