315 lines
9.6 KiB
YAML
315 lines
9.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Secure Digital Host Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: |
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This controller on Tegra family SoCs provides an interface for MMC, SD, and
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SDIO types of memory cards.
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This file documents differences between the core properties described by
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mmc-controller.yaml and the properties for the Tegra SDHCI controller.
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properties:
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compatible:
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oneOf:
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- enum:
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- nvidia,tegra20-sdhci
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- nvidia,tegra30-sdhci
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- nvidia,tegra114-sdhci
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- nvidia,tegra124-sdhci
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- nvidia,tegra210-sdhci
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- nvidia,tegra186-sdhci
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- nvidia,tegra194-sdhci
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- items:
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- const: nvidia,tegra132-sdhci
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- const: nvidia,tegra124-sdhci
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- items:
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- enum:
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- nvidia,tegra194-sdhci
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- nvidia,tegra234-sdhci
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- const: nvidia,tegra186-sdhci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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assigned-clocks: true
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assigned-clock-parents: true
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assigned-clock-rates: true
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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resets:
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items:
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- description: module reset
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reset-names:
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items:
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- const: sdhci
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power-gpios:
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description: specify GPIOs for power control
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maxItems: 1
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interconnects:
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items:
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- description: memory read client
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- description: memory write client
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interconnect-names:
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items:
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- const: dma-mem # read
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- const: write
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iommus:
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maxItems: 1
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operating-points-v2:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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power-domains:
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items:
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- description: phandle to the core power domain
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nvidia,default-tap:
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description: Specify the default inbound sampling clock trimmer value for
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non-tunable modes.
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The values are used for compensating trace length differences by
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adjusting the sampling point. The values are programmed to the Vendor
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Clock Control Register. Please refer to the reference manual of the SoC
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for correct values.
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The DQS trim values are only used on controllers which support HS400
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timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,default-trim:
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description: Specify the default outbound clock trimmer value.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,dqs-trim:
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description: Specify DQS trim value for HS400 timing.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-1v8:
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description: Specify drive strength calibration offsets for 1.8 V
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signaling modes.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-1v8-timeout:
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description: Specify drive strength used as a fallback in case the
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automatic calibration times out on a 1.8 V signaling mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-3v3:
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description: Specify drive strength calibration offsets for 3.3 V
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signaling modes.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-3v3-timeout:
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description: Specify drive strength used as a fallback in case the
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automatic calibration times out on a 3.3 V signaling mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-sdr104:
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description: Specify drive strength calibration offsets for SDR104 mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-down-offset-hs400:
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description: Specify drive strength calibration offsets for HS400 mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-1v8:
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description: Specify drive strength calibration offsets for 1.8 V
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signaling modes.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-1v8-timeout:
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description: Specify drive strength used as a fallback in case the
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automatic calibration times out on a 1.8 V signaling mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-3v3:
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description: Specify drive strength calibration offsets for 3.3 V
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signaling modes.
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The property values are drive codes which are programmed into the
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PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
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register. A higher value corresponds to higher drive strength. Please
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refer to the reference manual of the SoC for correct values. The SDR104
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and HS400 timing specific values are used in corresponding modes if
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specified.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-3v3-timeout:
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description: Specify drive strength used as a fallback in case the
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automatic calibration times out on a 3.3 V signaling mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-sdr104:
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description: Specify drive strength calibration offsets for SDR104 mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,pad-autocal-pull-up-offset-hs400:
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description: Specify drive strength calibration offsets for HS400 mode.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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nvidia,only-1-8v:
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description: The presence of this property indicates that the controller
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operates at a 1.8 V fixed I/O voltage.
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$ref: "/schemas/types.yaml#/definitions/flag"
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- resets
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- reset-names
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allOf:
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- $ref: "mmc-controller.yaml"
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra20-sdhci
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- nvidia,tegra30-sdhci
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- nvidia,tegra114-sdhci
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- nvidia,tegra124-sdhci
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then:
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properties:
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clocks:
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items:
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- description: module clock
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else:
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properties:
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clocks:
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items:
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- description: module clock
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- description: timeout clock
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clock-names:
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items:
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- const: sdhci
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- const: tmclk
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required:
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- clock-names
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra210-sdhci
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then:
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properties:
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pinctrl-names:
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oneOf:
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- items:
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- const: sdmmc-3v3
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description: pad configuration for 3.3 V
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- const: sdmmc-1v8
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description: pad configuration for 1.8 V
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- const: sdmmc-3v3-drv
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description: pull-up/down configuration for 3.3 V
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- const: sdmmc-1v8-drv
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description: pull-up/down configuration for 1.8 V
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- items:
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- const: sdmmc-3v3-drv
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description: pull-up/down configuration for 3.3 V
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- const: sdmmc-1v8-drv
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description: pull-up/down configuration for 1.8 V
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- items:
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- const: sdmmc-1v8-drv
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description: pull-up/down configuration for 1.8 V
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required:
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- clock-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra186-sdhci
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- nvidia,tegra194-sdhci
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then:
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properties:
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pinctrl-names:
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items:
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- const: sdmmc-3v3
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description: pad configuration for 3.3 V
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- const: sdmmc-1v8
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description: pad configuration for 1.8 V
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required:
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mmc@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = <47>;
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clocks = <&tegra_car 14>;
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 155 0>; /* gpio PT3 */
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bus-width = <8>;
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};
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mmc@700b0000 {
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compatible = "nvidia,tegra210-sdhci";
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reg = <0x700b0000 0x200>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
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<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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clock-names = "sdhci", "tmclk";
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
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"sdmmc-3v3-drv", "sdmmc-1v8-drv";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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pinctrl-2 = <&sdmmc1_3v3_drv>;
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pinctrl-3 = <&sdmmc1_1v8_drv>;
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nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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nvidia,default-tap = <0x2>;
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nvidia,default-trim = <0x4>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
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<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
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<&tegra_car TEGRA210_CLK_PLL_C4>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
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};
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