525 lines
12 KiB
YAML
525 lines
12 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos5433 SoC clock controller
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maintainers:
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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name::
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- "oscclk" - PLL input clock from XXTI
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/exynos5433.h header.
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properties:
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compatible:
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enum:
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# CMU_TOP which generates clocks for
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# IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
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# clocks
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- samsung,exynos5433-cmu-top
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# CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
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- samsung,exynos5433-cmu-cpif
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# CMU_MIF which generates clocks for DRAM Memory Controller domain
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- samsung,exynos5433-cmu-mif
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# CMU_PERIC which generates clocks for
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# UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
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- samsung,exynos5433-cmu-peric
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# CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
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- samsung,exynos5433-cmu-peris
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# CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
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- samsung,exynos5433-cmu-fsys
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- samsung,exynos5433-cmu-g2d
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# CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
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- samsung,exynos5433-cmu-disp
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- samsung,exynos5433-cmu-aud
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- samsung,exynos5433-cmu-bus0
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- samsung,exynos5433-cmu-bus1
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- samsung,exynos5433-cmu-bus2
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- samsung,exynos5433-cmu-g3d
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- samsung,exynos5433-cmu-gscl
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- samsung,exynos5433-cmu-apollo
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# CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
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# CoreSight and L2 cache controller
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- samsung,exynos5433-cmu-atlas
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# CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
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# JPEG IPs
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- samsung,exynos5433-cmu-mscl
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- samsung,exynos5433-cmu-mfc
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- samsung,exynos5433-cmu-hevc
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# CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
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- samsung,exynos5433-cmu-isp
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# CMU_CAM0 which generates clocks for
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# MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
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- samsung,exynos5433-cmu-cam0
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# CMU_CAM1 which generates clocks for
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# Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
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- samsung,exynos5433-cmu-cam1
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# CMU_IMEM which generates clocks for SSS (Security SubSystem) and
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# SlimSSS IPs
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- samsung,exynos5433-cmu-imem
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clocks:
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minItems: 1
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maxItems: 10
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clock-names:
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minItems: 1
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maxItems: 10
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"#clock-cells":
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const: 1
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- "#clock-cells"
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-top
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: oscclk
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- const: sclk_mphy_pll
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- const: sclk_mfc_pll
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- const: sclk_bus_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-cpif
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 1
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clock-names:
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items:
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- const: oscclk
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-mif
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: sclk_mphy_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-fsys
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then:
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properties:
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clocks:
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minItems: 10
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maxItems: 10
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clock-names:
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items:
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- const: oscclk
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- const: sclk_ufs_mphy
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- const: aclk_fsys_200
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- const: sclk_pcie_100_fsys
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- const: sclk_ufsunipro_fsys
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- const: sclk_mmc2_fsys
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- const: sclk_mmc1_fsys
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- const: sclk_mmc0_fsys
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- const: sclk_usbhost30_fsys
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- const: sclk_usbdrd30_fsys
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-g2d
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: oscclk
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- const: aclk_g2d_266
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- const: aclk_g2d_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-disp
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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items:
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- const: oscclk
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- const: sclk_dsim1_disp
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- const: sclk_dsim0_disp
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- const: sclk_dsd_disp
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- const: sclk_decon_tv_eclk_disp
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- const: sclk_decon_vclk_disp
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- const: sclk_decon_eclk_disp
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- const: sclk_decon_tv_vclk_disp
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- const: aclk_disp_333
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-aud
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: fout_aud_pll
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-bus0
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 1
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clock-names:
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items:
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- const: aclk_bus0_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-bus1
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 1
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clock-names:
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items:
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- const: aclk_bus1_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-bus2
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: aclk_bus2_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-g3d
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: aclk_g3d_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-gscl
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: oscclk
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- const: aclk_gscl_111
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- const: aclk_gscl_333
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-apollo
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: sclk_bus_pll_apollo
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-atlas
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: sclk_bus_pll_atlas
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-mscl
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: oscclk
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- const: sclk_jpeg_mscl
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- const: aclk_mscl_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-mfc
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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- const: aclk_mfc_400
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required:
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- clock-names
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- clocks
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5433-cmu-hevc
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: oscclk
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||
|
|
- const: aclk_hevc_400
|
||
|
|
required:
|
||
|
|
- clock-names
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
- if:
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
contains:
|
||
|
|
const: samsung,exynos5433-cmu-isp
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
clocks:
|
||
|
|
minItems: 3
|
||
|
|
maxItems: 3
|
||
|
|
clock-names:
|
||
|
|
items:
|
||
|
|
- const: oscclk
|
||
|
|
- const: aclk_isp_dis_400
|
||
|
|
- const: aclk_isp_400
|
||
|
|
required:
|
||
|
|
- clock-names
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
- if:
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
contains:
|
||
|
|
const: samsung,exynos5433-cmu-cam0
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
clocks:
|
||
|
|
minItems: 4
|
||
|
|
maxItems: 4
|
||
|
|
clock-names:
|
||
|
|
items:
|
||
|
|
- const: oscclk
|
||
|
|
- const: aclk_cam0_333
|
||
|
|
- const: aclk_cam0_400
|
||
|
|
- const: aclk_cam0_552
|
||
|
|
required:
|
||
|
|
- clock-names
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
- if:
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
contains:
|
||
|
|
const: samsung,exynos5433-cmu-cam1
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
clocks:
|
||
|
|
minItems: 7
|
||
|
|
maxItems: 7
|
||
|
|
clock-names:
|
||
|
|
items:
|
||
|
|
- const: oscclk
|
||
|
|
- const: sclk_isp_uart_cam1
|
||
|
|
- const: sclk_isp_spi1_cam1
|
||
|
|
- const: sclk_isp_spi0_cam1
|
||
|
|
- const: aclk_cam1_333
|
||
|
|
- const: aclk_cam1_400
|
||
|
|
- const: aclk_cam1_552
|
||
|
|
required:
|
||
|
|
- clock-names
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
- if:
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
contains:
|
||
|
|
const: samsung,exynos5433-cmu-imem
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
clocks:
|
||
|
|
minItems: 4
|
||
|
|
maxItems: 4
|
||
|
|
clock-names:
|
||
|
|
items:
|
||
|
|
- const: oscclk
|
||
|
|
- const: aclk_imem_sssx_266
|
||
|
|
- const: aclk_imem_266
|
||
|
|
- const: aclk_imem_200
|
||
|
|
required:
|
||
|
|
- clock-names
|
||
|
|
- clocks
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
#include <dt-bindings/clock/exynos5433.h>
|
||
|
|
xxti: clock {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-output-names = "oscclk";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <24000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clock-controller@10030000 {
|
||
|
|
compatible = "samsung,exynos5433-cmu-top";
|
||
|
|
reg = <0x10030000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
|
||
|
|
clock-names = "oscclk",
|
||
|
|
"sclk_mphy_pll",
|
||
|
|
"sclk_mfc_pll",
|
||
|
|
"sclk_bus_pll";
|
||
|
|
clocks = <&xxti>,
|
||
|
|
<&cmu_cpif CLK_SCLK_MPHY_PLL>,
|
||
|
|
<&cmu_mif CLK_SCLK_MFC_PLL>,
|
||
|
|
<&cmu_mif CLK_SCLK_BUS_PLL>;
|
||
|
|
};
|