79 lines
2.4 KiB
YAML
79 lines
2.4 KiB
YAML
|
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Rockchip RK3368 Clock and Reset Unit (CRU)
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Elaine Zhang <zhangqing@rock-chips.com>
|
||
|
|
- Heiko Stuebner <heiko@sntech.de>
|
||
|
|
|
||
|
|
description: |
|
||
|
|
The RK3368 clock controller generates and supplies clocks to various
|
||
|
|
controllers within the SoC and also implements a reset controller for SoC
|
||
|
|
peripherals.
|
||
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
||
|
|
to specify the clock which they consume. All available clocks are defined as
|
||
|
|
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||
|
|
used in device tree sources. Similar macros exist for the reset sources in
|
||
|
|
these files.
|
||
|
|
There are several clocks that are generated outside the SoC. It is expected
|
||
|
|
that they are defined using standard clock bindings with following
|
||
|
|
clock-output-names:
|
||
|
|
- "xin24m" - crystal input - required
|
||
|
|
- "xin32k" - rtc clock - optional
|
||
|
|
- "ext_i2s" - external I2S clock - optional
|
||
|
|
- "ext_gmac" - external GMAC clock - optional
|
||
|
|
- "ext_hsadc" - external HSADC clock - optional
|
||
|
|
- "ext_isp" - external ISP clock - optional
|
||
|
|
- "ext_jtag" - external JTAG clock - optional
|
||
|
|
- "ext_vip" - external VIP clock - optional
|
||
|
|
- "usbotg_out" - output clock of the pll in the otg phy
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
enum:
|
||
|
|
- rockchip,rk3368-cru
|
||
|
|
|
||
|
|
reg:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
"#clock-cells":
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
"#reset-cells":
|
||
|
|
const: 1
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
maxItems: 1
|
||
|
|
|
||
|
|
clock-names:
|
||
|
|
const: xin24m
|
||
|
|
|
||
|
|
rockchip,grf:
|
||
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
||
|
|
description:
|
||
|
|
Phandle to the syscon managing the "general register files" (GRF),
|
||
|
|
if missing pll rates are not changeable, due to the missing pll
|
||
|
|
lock status.
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- "#clock-cells"
|
||
|
|
- "#reset-cells"
|
||
|
|
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
cru: clock-controller@ff760000 {
|
||
|
|
compatible = "rockchip,rk3368-cru";
|
||
|
|
reg = <0xff760000 0x1000>;
|
||
|
|
rockchip,grf = <&grf>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|