91 lines
2.2 KiB
YAML
91 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
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maintainers:
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- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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description: |
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The CS2000-CP is an extremely versatile system clocking device that
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utilizes a programmable phase lock loop.
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Link: https://www.cirrus.com/products/cs2000/
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properties:
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compatible:
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enum:
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- cirrus,cs2000-cp
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clocks:
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description:
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Common clock binding for CLK_IN, XTI/REF_CLK
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maxItems: 2
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clock-names:
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items:
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- const: clk_in
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- const: ref_clk
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'#clock-cells':
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const: 0
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reg:
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maxItems: 1
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cirrus,aux-output-source:
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description:
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Specifies the function of the auxiliary clock output pin
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
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- 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
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- 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
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- 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
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default: 0
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cirrus,clock-skip:
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description:
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This mode allows the PLL to maintain lock even when CLK_IN
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has missing pulses for up to 20 ms.
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$ref: /schemas/types.yaml#/definitions/flag
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cirrus,dynamic-mode:
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description:
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In dynamic mode, the CLK_IN input is used to drive the
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digital PLL of the silicon.
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If not given, the static mode shall be used to derive the
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output signal directly from the REF_CLK input.
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$ref: /schemas/types.yaml#/definitions/flag
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/cirrus,cs2000-cp.h>
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i2c@0 {
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reg = <0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-controller@4f {
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#clock-cells = <0>;
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compatible = "cirrus,cs2000-cp";
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reg = <0x4f>;
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clocks = <&rcar_sound 0>, <&x12_clk>;
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clock-names = "clk_in", "ref_clk";
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cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;
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};
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};
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