60 lines
1.9 KiB
Plaintext
60 lines
1.9 KiB
Plaintext
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* Amlogic AXG Audio Clock Controllers
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The Amlogic AXG audio clock controller generates and supplies clock to the
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other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
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devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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"amlogic,g12a-audio-clkc" for G12A,
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"amlogic,sm1-audio-clkc" for S905X3.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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in clock-names.
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- clock-names : must contain the following:
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* "pclk" - Main peripheral bus clock
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may contain the following:
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* "mst_in[0-7]" - 8 input plls to generate clock signals
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* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
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components.
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* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
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components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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- #reset-cells : should be 1 on the g12a (and following) soc family
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
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used in device tree sources.
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Example:
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clkc_audio: clock-controller@0 {
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compatible = "amlogic,axg-audio-clkc";
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reg = <0x0 0x0 0x0 0xb4>;
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#clock-cells = <1>;
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clocks = <&clkc CLKID_AUDIO>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL3>,
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<&clkc CLKID_HIFI_PLL>,
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<&clkc CLKID_FCLK_DIV3>,
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_GP0_PLL>;
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clock-names = "pclk",
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"mst_in0",
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"mst_in1",
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"mst_in2",
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"mst_in3",
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"mst_in4",
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"mst_in5",
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"mst_in6",
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"mst_in7";
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resets = <&reset RESET_AUDIO>;
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};
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