946 lines
28 KiB
JSON
946 lines
28 KiB
JSON
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[
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||
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{
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||
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"BriefDescription": "Cycles the divider is busy",
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"Counter": "0,1,2,3",
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"EventCode": "0x14",
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||
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"EventName": "ARITH.CYCLES_DIV_BUSY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Divide Operations executed",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EdgeDetect": "1",
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"EventCode": "0x14",
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"EventName": "ARITH.DIV",
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||
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"Invert": "1",
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||
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"SampleAfterValue": "2000000",
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||
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"UMask": "0x1"
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},
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||
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{
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"BriefDescription": "Multiply operations executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x14",
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||
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"EventName": "ARITH.MUL",
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||
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"SampleAfterValue": "2000000",
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||
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"UMask": "0x2"
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},
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||
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{
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"BriefDescription": "BACLEAR asserted with bad target address",
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"Counter": "0,1,2,3",
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"EventCode": "0xE6",
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"EventName": "BACLEAR.BAD_TARGET",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "BACLEAR asserted, regardless of cause",
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"Counter": "0,1,2,3",
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"EventCode": "0xE6",
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"EventName": "BACLEAR.CLEAR",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Instruction queue forced BACLEAR",
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"Counter": "0,1,2,3",
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"EventCode": "0xA7",
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"EventName": "BACLEAR_FORCE_IQ",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Early Branch Prediciton Unit clears",
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"Counter": "0,1,2,3",
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"EventCode": "0xE8",
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"EventName": "BPU_CLEARS.EARLY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Late Branch Prediction Unit clears",
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"Counter": "0,1,2,3",
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"EventCode": "0xE8",
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"EventName": "BPU_CLEARS.LATE",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Branch prediction unit missed call or return",
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"Counter": "0,1,2,3",
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"EventCode": "0xE5",
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"EventName": "BPU_MISSED_CALL_RET",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Branch instructions decoded",
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"Counter": "0,1,2,3",
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"EventCode": "0xE0",
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"EventName": "BR_INST_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Branch instructions executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x7f"
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},
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{
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"BriefDescription": "Conditional branch instructions executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.COND",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Unconditional branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.DIRECT",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Unconditional call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
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"SampleAfterValue": "20000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Indirect call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
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"SampleAfterValue": "20000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Indirect non call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
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"SampleAfterValue": "20000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.NEAR_CALLS",
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"SampleAfterValue": "20000",
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"UMask": "0x30"
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},
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{
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"BriefDescription": "All non call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.NON_CALLS",
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"SampleAfterValue": "200000",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Indirect return branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.RETURN_NEAR",
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"SampleAfterValue": "20000",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Taken branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x88",
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"EventName": "BR_INST_EXEC.TAKEN",
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"SampleAfterValue": "200000",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Retired branch instructions (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Retired conditional branch instructions (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.CONDITIONAL",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Retired near call instructions (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.NEAR_CALL",
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"PEBS": "1",
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"SampleAfterValue": "20000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Mispredicted branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.ANY",
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"SampleAfterValue": "20000",
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"UMask": "0x7f"
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},
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{
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"BriefDescription": "Mispredicted conditional branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.COND",
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"SampleAfterValue": "20000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Mispredicted unconditional branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.DIRECT",
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"SampleAfterValue": "20000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Mispredicted non call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
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"SampleAfterValue": "2000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Mispredicted indirect call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
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"SampleAfterValue": "2000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Mispredicted indirect non call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
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"SampleAfterValue": "2000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Mispredicted call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.NEAR_CALLS",
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"SampleAfterValue": "2000",
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"UMask": "0x30"
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},
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{
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||
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"BriefDescription": "Mispredicted non call branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.NON_CALLS",
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"SampleAfterValue": "20000",
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||
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Mispredicted return branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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||
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"EventName": "BR_MISP_EXEC.RETURN_NEAR",
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"SampleAfterValue": "2000",
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||
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"UMask": "0x8"
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},
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||
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{
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||
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"BriefDescription": "Mispredicted taken branches executed",
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"Counter": "0,1,2,3",
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"EventCode": "0x89",
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"EventName": "BR_MISP_EXEC.TAKEN",
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"SampleAfterValue": "20000",
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"UMask": "0x40"
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},
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||
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{
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||
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"BriefDescription": "Mispredicted near retired calls (Precise Event)",
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"Counter": "0,1,2,3",
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||
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"EventCode": "0xC5",
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||
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"EventName": "BR_MISP_RETIRED.NEAR_CALL",
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"PEBS": "1",
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||
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"SampleAfterValue": "2000",
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||
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"UMask": "0x2"
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||
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},
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||
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{
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||
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"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
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||
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"Counter": "Fixed counter 3",
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||
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"EventCode": "0x0",
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||
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"EventName": "CPU_CLK_UNHALTED.REF",
|
||
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"SampleAfterValue": "2000000",
|
||
|
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"UMask": "0x0"
|
||
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},
|
||
|
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{
|
||
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"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
|
||
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"Counter": "0,1,2,3",
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||
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"EventCode": "0x3C",
|
||
|
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"EventName": "CPU_CLK_UNHALTED.REF_P",
|
||
|
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"SampleAfterValue": "100000",
|
||
|
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"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
|
||
|
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"Counter": "Fixed counter 2",
|
||
|
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"EventCode": "0x0",
|
||
|
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"EventName": "CPU_CLK_UNHALTED.THREAD",
|
||
|
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"SampleAfterValue": "2000000",
|
||
|
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"UMask": "0x0"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x3C",
|
||
|
|
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
|
||
|
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"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x0"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Total CPU cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "2",
|
||
|
|
"EventCode": "0x3C",
|
||
|
|
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x0"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Any Instruction Length Decoder stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x87",
|
||
|
|
"EventName": "ILD_STALL.ANY",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0xf"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Instruction Queue full stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x87",
|
||
|
|
"EventName": "ILD_STALL.IQ_FULL",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Length Change Prefix stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x87",
|
||
|
|
"EventName": "ILD_STALL.LCP",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Stall cycles due to BPU MRU bypass",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x87",
|
||
|
|
"EventName": "ILD_STALL.MRU",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Regen stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x87",
|
||
|
|
"EventName": "ILD_STALL.REGEN",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Instructions that must be decoded by decoder 0",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x18",
|
||
|
|
"EventName": "INST_DECODED.DEC0",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Instructions written to instruction queue.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x17",
|
||
|
|
"EventName": "INST_QUEUE_WRITES",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles instructions are written to the instruction queue",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x1E",
|
||
|
|
"EventName": "INST_QUEUE_WRITE_CYCLES",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Instructions retired (fixed counter)",
|
||
|
|
"Counter": "Fixed counter 1",
|
||
|
|
"EventCode": "0x0",
|
||
|
|
"EventName": "INST_RETIRED.ANY",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x0"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC0",
|
||
|
|
"EventName": "INST_RETIRED.ANY_P",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Retired MMX instructions (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC0",
|
||
|
|
"EventName": "INST_RETIRED.MMX",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Total cycles (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "16",
|
||
|
|
"EventCode": "0xC0",
|
||
|
|
"EventName": "INST_RETIRED.TOTAL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Total cycles (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "16",
|
||
|
|
"EventCode": "0xC0",
|
||
|
|
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
|
||
|
|
"Invert": "1",
|
||
|
|
"PEBS": "2",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Retired floating-point operations (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC0",
|
||
|
|
"EventName": "INST_RETIRED.X87",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Load operations conflicting with software prefetches",
|
||
|
|
"Counter": "0,1",
|
||
|
|
"EventCode": "0x4C",
|
||
|
|
"EventName": "LOAD_HIT_PRE",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles when uops were delivered by the LSD",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xA8",
|
||
|
|
"EventName": "LSD.ACTIVE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles no uops were delivered by the LSD",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xA8",
|
||
|
|
"EventName": "LSD.INACTIVE",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Loops that can't stream from the instruction queue",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0x20",
|
||
|
|
"EventName": "LSD_OVERFLOW",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles machine clear asserted",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC3",
|
||
|
|
"EventName": "MACHINE_CLEARS.CYCLES",
|
||
|
|
"SampleAfterValue": "20000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC3",
|
||
|
|
"EventName": "MACHINE_CLEARS.MEM_ORDER",
|
||
|
|
"SampleAfterValue": "20000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Self-Modifying Code detected",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC3",
|
||
|
|
"EventName": "MACHINE_CLEARS.SMC",
|
||
|
|
"SampleAfterValue": "20000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "All RAT stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD2",
|
||
|
|
"EventName": "RAT_STALLS.ANY",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0xf"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Flag stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD2",
|
||
|
|
"EventName": "RAT_STALLS.FLAGS",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Partial register stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD2",
|
||
|
|
"EventName": "RAT_STALLS.REGISTERS",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "ROB read port stalls cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD2",
|
||
|
|
"EventName": "RAT_STALLS.ROB_READ_PORT",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Scoreboard stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD2",
|
||
|
|
"EventName": "RAT_STALLS.SCOREBOARD",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Resource related stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.ANY",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "FPU control word write stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.FPCW",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x20"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Load buffer stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.LOAD",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "MXCSR rename stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.MXCSR",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x40"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Other Resource related stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.OTHER",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x80"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "ROB full stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.ROB_FULL",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Reservation Station full stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.RS_FULL",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Store buffer stall cycles",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xA2",
|
||
|
|
"EventName": "RESOURCE_STALLS.STORE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC7",
|
||
|
|
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC7",
|
||
|
|
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC7",
|
||
|
|
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC7",
|
||
|
|
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC7",
|
||
|
|
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "200000",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Stack pointer instructions decoded",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD1",
|
||
|
|
"EventName": "UOPS_DECODED.ESP_FOLDING",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Stack pointer sync operations",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xD1",
|
||
|
|
"EventName": "UOPS_DECODED.ESP_SYNC",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops decoded by Microcode Sequencer",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xD1",
|
||
|
|
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles no Uops are decoded",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xD1",
|
||
|
|
"EventName": "UOPS_DECODED.STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles Uops executed on any port (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x3f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops executed on any port (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EdgeDetect": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x3f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops executed on ports 0-4 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EdgeDetect": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles no Uops issued on any port (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x3f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1f"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops executed on port 0",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT0",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops issued on ports 0, 1 or 5",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT015",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x40"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x40"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops executed on port 1",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops issued on ports 2, 3 or 4",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT234_CORE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x80"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops executed on port 2 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT2_CORE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops executed on port 3 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT3_CORE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Uops executed on port 4 (core count)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT4_CORE",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops executed on port 5",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xB1",
|
||
|
|
"EventName": "UOPS_EXECUTED.PORT5",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x20"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops issued",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xE",
|
||
|
|
"EventName": "UOPS_ISSUED.ANY",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles no Uops were issued on any thread",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xE",
|
||
|
|
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"AnyThread": "1",
|
||
|
|
"BriefDescription": "Cycles Uops were issued on either thread",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xE",
|
||
|
|
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Fused Uops issued",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xE",
|
||
|
|
"EventName": "UOPS_ISSUED.FUSED",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles no Uops were issued",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xE",
|
||
|
|
"EventName": "UOPS_ISSUED.STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles Uops are being retired",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.ANY",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.MACRO_FUSED",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Retirement slots used (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.STALL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterMask": "16",
|
||
|
|
"EventCode": "0xC2",
|
||
|
|
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
|
||
|
|
"Invert": "1",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Uop unfusions due to FP exceptions",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventCode": "0xDB",
|
||
|
|
"EventName": "UOP_UNFUSION",
|
||
|
|
"SampleAfterValue": "2000000",
|
||
|
|
"UMask": "0x1"
|
||
|
|
}
|
||
|
|
]
|