255 lines
8.7 KiB
JSON
255 lines
8.7 KiB
JSON
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[
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{
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"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
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"CollectPEBSRecord": "2",
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"Counter": "33",
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"EventName": "CPU_CLK_UNHALTED.CORE",
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"PEBScounters": "33",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x3c",
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"EventName": "CPU_CLK_UNHALTED.CORE_P",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
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"CollectPEBSRecord": "2",
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"Counter": "34",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC",
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"PEBScounters": "34",
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"SampleAfterValue": "2000003",
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"UMask": "0x3",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
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"CollectPEBSRecord": "2",
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"Counter": "33",
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"EventName": "CPU_CLK_UNHALTED.THREAD",
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"PEBScounters": "33",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x3c",
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"EventName": "CPU_CLK_UNHALTED.THREAD_P",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
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"CollectPEBSRecord": "2",
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"Counter": "32",
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"EventName": "INST_RETIRED.ANY",
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"PEBS": "1",
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"PEBScounters": "32",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of instructions retired",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc0",
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"EventName": "INST_RETIRED.ANY_P",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x73",
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"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x74",
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"EventName": "TOPDOWN_BE_BOUND.ALL",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x71",
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"EventName": "TOPDOWN_FE_BOUND.ALL",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x72",
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"EventName": "TOPDOWN_RETIRING.ALL",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "All branch instructions retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "400009",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "All mispredicted branch instructions retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "400009",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Reference cycles when the core is not in halt state.",
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"CollectPEBSRecord": "2",
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"Counter": "34",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC",
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"PEBScounters": "34",
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"SampleAfterValue": "2000003",
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"UMask": "0x3",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Reference cycles when the core is not in halt state.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x3c",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Core cycles when the thread is not in halt state",
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"CollectPEBSRecord": "2",
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"Counter": "33",
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"EventName": "CPU_CLK_UNHALTED.THREAD",
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"PEBScounters": "33",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Thread cycles when thread is not in halt state",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x3c",
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"EventName": "CPU_CLK_UNHALTED.THREAD_P",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
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"CollectPEBSRecord": "2",
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"Counter": "32",
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"EventName": "INST_RETIRED.ANY",
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"PEBS": "1",
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"PEBScounters": "32",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of instructions retired. General Counter - architectural event",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc0",
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"EventName": "INST_RETIRED.ANY_P",
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"PEBS": "1",
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"PEBScounters": "1,2,3,4,5,6,7",
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"SampleAfterValue": "2000003",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x03",
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"EventName": "LD_BLOCKS.STORE_FORWARD",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "100003",
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"UMask": "0x82",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
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"CollectPEBSRecord": "2",
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"Counter": "35",
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"EventName": "TOPDOWN.SLOTS",
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"PEBScounters": "35",
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"SampleAfterValue": "10000003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xa4",
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"EventName": "TOPDOWN.SLOTS_P",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "10000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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}
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]
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