59 lines
2.1 KiB
JSON
59 lines
2.1 KiB
JSON
|
[
|
||
|
|
{
|
||
|
|
"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5C",
|
||
|
|
"EventName": "CPL_CYCLES.RING0",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EdgeDetect": "1",
|
||
|
|
"EventCode": "0x5C",
|
||
|
|
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||
|
|
"SampleAfterValue": "100007",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5C",
|
||
|
|
"EventName": "CPL_CYCLES.RING123",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x4E",
|
||
|
|
"EventName": "HW_PRE_REQ.DL1_MISS",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Valid instructions written to IQ per cycle.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x17",
|
||
|
|
"EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x63",
|
||
|
|
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
}
|
||
|
|
]
|