125 lines
3.5 KiB
JSON
125 lines
3.5 KiB
JSON
|
[
|
||
|
{
|
||
|
"BriefDescription": "Memory accesses that missed the DTLB.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x8",
|
||
|
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x7"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "DTLB misses due to load operations.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x8",
|
||
|
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x5"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "DTLB misses due to store operations.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x8",
|
||
|
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x6"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "L0 DTLB misses due to load operations.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x8",
|
||
|
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x9"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "L0 DTLB misses due to store operations",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x8",
|
||
|
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0xa"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "ITLB flushes.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x82",
|
||
|
"EventName": "ITLB.FLUSH",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x4"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "ITLB hits.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x82",
|
||
|
"EventName": "ITLB.HIT",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x1"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "ITLB misses.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0x82",
|
||
|
"EventName": "ITLB.MISSES",
|
||
|
"PEBS": "2",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x2"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Retired loads that miss the DTLB (precise event).",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xCB",
|
||
|
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
|
||
|
"PEBS": "1",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x4"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Duration of page-walks in core cycles",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.CYCLES",
|
||
|
"SampleAfterValue": "2000000",
|
||
|
"UMask": "0x3"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Duration of D-side only page walks",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
|
||
|
"SampleAfterValue": "2000000",
|
||
|
"UMask": "0x1"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Number of D-side only page walks",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x1"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Duration of I-Side page walks",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
|
||
|
"SampleAfterValue": "2000000",
|
||
|
"UMask": "0x2"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Number of I-Side page walks",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x2"
|
||
|
},
|
||
|
{
|
||
|
"BriefDescription": "Number of page-walks executed.",
|
||
|
"Counter": "0,1",
|
||
|
"EventCode": "0xC",
|
||
|
"EventName": "PAGE_WALKS.WALKS",
|
||
|
"SampleAfterValue": "200000",
|
||
|
"UMask": "0x3"
|
||
|
}
|
||
|
]
|