81 lines
2.6 KiB
C
81 lines
2.6 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* Copyright (c) 2022 MediaTek Corporation. All rights reserved.
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*
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* Header file for the mt8186 DSP register definition
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*/
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#ifndef __MT8186_H
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#define __MT8186_H
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struct mtk_adsp_chip_info;
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struct snd_sof_dev;
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#define DSP_REG_BAR 4
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#define DSP_SECREG_BAR 5
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#define DSP_BUSREG_BAR 6
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/*****************************************************************************
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* R E G I S T E R TABLE
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*****************************************************************************/
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/* dsp cfg */
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#define ADSP_CFGREG_SW_RSTN 0x0000
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#define SW_DBG_RSTN_C0 BIT(0)
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#define SW_RSTN_C0 BIT(4)
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#define ADSP_HIFI_IO_CONFIG 0x000C
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#define TRACEMEMREADY BIT(15)
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#define RUNSTALL BIT(31)
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#define ADSP_IRQ_MASK 0x0030
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#define ADSP_DVFSRC_REQ 0x0040
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#define ADSP_DDREN_REQ_0 0x0044
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#define ADSP_SEMAPHORE 0x0064
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#define ADSP_WDT_CON_C0 0x007C
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#define ADSP_MBOX_IRQ_EN 0x009C
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#define DSP_MBOX0_IRQ_EN BIT(0)
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#define DSP_MBOX1_IRQ_EN BIT(1)
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#define DSP_MBOX2_IRQ_EN BIT(2)
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#define DSP_MBOX3_IRQ_EN BIT(3)
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#define DSP_MBOX4_IRQ_EN BIT(4)
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#define DSP_PDEBUGPC 0x013C
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#define ADSP_CK_EN 0x1000
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#define CORE_CLK_EN BIT(0)
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#define COREDBG_EN BIT(1)
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#define TIMER_EN BIT(3)
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#define DMA_EN BIT(4)
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#define UART_EN BIT(5)
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#define ADSP_UART_CTRL 0x1010
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#define UART_BCLK_CG BIT(0)
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#define UART_RSTN BIT(3)
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/* dsp sec */
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#define ADSP_PRID 0x0
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#define ADSP_ALTVEC_C0 0x04
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#define ADSP_ALTVECSEL 0x0C
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#define ADSP_ALTVECSEL_C0 BIT(1)
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/* dsp bus */
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#define ADSP_SRAM_POOL_CON 0x190
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#define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */
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#define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */
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#define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */
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/* DSP memories */
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#define MBOX_OFFSET 0x500000 /* DRAM */
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#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */
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#define DSP_DRAM_SIZE 0xA00000 /* 16M */
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/*remap dram between AP and DSP view, 4KB aligned*/
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#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */
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#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */
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#define DRAM_REMAP_SHIFT 12
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#define DRAM_REMAP_MASK 0xFFF
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#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/
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#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/
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#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)
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void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
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void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
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#endif
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