99 lines
2.0 KiB
C
99 lines
2.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt2701-afe-common.h -- Mediatek 2701 audio driver definitions
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Garlic Tseng <garlic.tseng@mediatek.com>
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*/
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#ifndef _MT_2701_AFE_COMMON_H_
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#define _MT_2701_AFE_COMMON_H_
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#include <sound/soc.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include "mt2701-reg.h"
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#include "../common/mtk-base-afe.h"
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#define MT2701_PLL_DOMAIN_0_RATE 98304000
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#define MT2701_PLL_DOMAIN_1_RATE 90316800
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enum {
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MT2701_MEMIF_DL1,
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MT2701_MEMIF_DL2,
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MT2701_MEMIF_DL3,
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MT2701_MEMIF_DL4,
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MT2701_MEMIF_DL5,
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MT2701_MEMIF_DL_SINGLE_NUM,
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MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
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MT2701_MEMIF_UL1,
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MT2701_MEMIF_UL2,
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MT2701_MEMIF_UL3,
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MT2701_MEMIF_UL4,
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MT2701_MEMIF_UL5,
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MT2701_MEMIF_DLBT,
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MT2701_MEMIF_ULBT,
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MT2701_MEMIF_NUM,
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MT2701_IO_I2S = MT2701_MEMIF_NUM,
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MT2701_IO_2ND_I2S,
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MT2701_IO_3RD_I2S,
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MT2701_IO_4TH_I2S,
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MT2701_IO_5TH_I2S,
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MT2701_IO_6TH_I2S,
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MT2701_IO_MRG,
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};
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enum {
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MT2701_IRQ_ASYS_IRQ1,
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MT2701_IRQ_ASYS_IRQ2,
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MT2701_IRQ_ASYS_IRQ3,
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MT2701_IRQ_ASYS_END,
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};
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enum audio_base_clock {
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MT2701_INFRA_SYS_AUDIO,
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MT2701_TOP_AUD_MCLK_SRC0,
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MT2701_TOP_AUD_MCLK_SRC1,
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MT2701_TOP_AUD_A1SYS,
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MT2701_TOP_AUD_A2SYS,
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MT2701_AUDSYS_AFE,
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MT2701_AUDSYS_AFE_CONN,
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MT2701_AUDSYS_A1SYS,
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MT2701_AUDSYS_A2SYS,
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MT2701_BASE_CLK_NUM,
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};
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struct mt2701_i2s_data {
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int i2s_ctrl_reg;
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int i2s_asrc_fs_shift;
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int i2s_asrc_fs_mask;
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};
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struct mt2701_i2s_path {
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int mclk_rate;
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int on[MTK_STREAM_NUM];
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int occupied[MTK_STREAM_NUM];
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const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
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struct clk *hop_ck[MTK_STREAM_NUM];
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struct clk *sel_ck;
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struct clk *div_ck;
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struct clk *mclk_ck;
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struct clk *asrco_ck;
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};
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struct mt2701_soc_variants {
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bool has_one_heart_mode;
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int i2s_num;
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};
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struct mt2701_afe_private {
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struct mt2701_i2s_path *i2s_path;
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struct clk *base_ck[MT2701_BASE_CLK_NUM];
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struct clk *mrgif_ck;
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bool mrg_enable[MTK_STREAM_NUM];
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const struct mt2701_soc_variants *soc;
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};
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#endif
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