244 lines
8.1 KiB
C
244 lines
8.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Code Loader DMA support
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*
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* Copyright (C) 2015, Intel Corporation.
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*/
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#ifndef SKL_SST_CLDMA_H_
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#define SKL_SST_CLDMA_H_
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#define FW_CL_STREAM_NUMBER 0x1
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#define DMA_ADDRESS_128_BITS_ALIGNMENT 7
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#define BDL_ALIGN(x) (x >> DMA_ADDRESS_128_BITS_ALIGNMENT)
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#define SKL_ADSPIC_CL_DMA 0x2
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#define SKL_ADSPIS_CL_DMA 0x2
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#define SKL_CL_DMA_SD_INT_DESC_ERR 0x10 /* Descriptor error interrupt */
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#define SKL_CL_DMA_SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
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#define SKL_CL_DMA_SD_INT_COMPLETE 0x04 /* Buffer completion interrupt */
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/* Intel HD Audio Code Loader DMA Registers */
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#define HDA_ADSP_LOADER_BASE 0x80
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/* Stream Registers */
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#define SKL_ADSP_REG_CL_SD_CTL (HDA_ADSP_LOADER_BASE + 0x00)
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#define SKL_ADSP_REG_CL_SD_STS (HDA_ADSP_LOADER_BASE + 0x03)
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#define SKL_ADSP_REG_CL_SD_LPIB (HDA_ADSP_LOADER_BASE + 0x04)
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#define SKL_ADSP_REG_CL_SD_CBL (HDA_ADSP_LOADER_BASE + 0x08)
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#define SKL_ADSP_REG_CL_SD_LVI (HDA_ADSP_LOADER_BASE + 0x0c)
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#define SKL_ADSP_REG_CL_SD_FIFOW (HDA_ADSP_LOADER_BASE + 0x0e)
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#define SKL_ADSP_REG_CL_SD_FIFOSIZE (HDA_ADSP_LOADER_BASE + 0x10)
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#define SKL_ADSP_REG_CL_SD_FORMAT (HDA_ADSP_LOADER_BASE + 0x12)
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#define SKL_ADSP_REG_CL_SD_FIFOL (HDA_ADSP_LOADER_BASE + 0x14)
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#define SKL_ADSP_REG_CL_SD_BDLPL (HDA_ADSP_LOADER_BASE + 0x18)
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#define SKL_ADSP_REG_CL_SD_BDLPU (HDA_ADSP_LOADER_BASE + 0x1c)
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/* CL: Software Position Based FIFO Capability Registers */
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#define SKL_ADSP_REG_CL_SPBFIFO (HDA_ADSP_LOADER_BASE + 0x20)
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#define SKL_ADSP_REG_CL_SPBFIFO_SPBFCH (SKL_ADSP_REG_CL_SPBFIFO + 0x0)
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#define SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL (SKL_ADSP_REG_CL_SPBFIFO + 0x4)
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#define SKL_ADSP_REG_CL_SPBFIFO_SPIB (SKL_ADSP_REG_CL_SPBFIFO + 0x8)
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#define SKL_ADSP_REG_CL_SPBFIFO_MAXFIFOS (SKL_ADSP_REG_CL_SPBFIFO + 0xc)
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/* CL: Stream Descriptor x Control */
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/* Stream Reset */
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#define CL_SD_CTL_SRST_SHIFT 0
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#define CL_SD_CTL_SRST_MASK (1 << CL_SD_CTL_SRST_SHIFT)
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#define CL_SD_CTL_SRST(x) \
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((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)
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/* Stream Run */
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#define CL_SD_CTL_RUN_SHIFT 1
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#define CL_SD_CTL_RUN_MASK (1 << CL_SD_CTL_RUN_SHIFT)
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#define CL_SD_CTL_RUN(x) \
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((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)
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/* Interrupt On Completion Enable */
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#define CL_SD_CTL_IOCE_SHIFT 2
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#define CL_SD_CTL_IOCE_MASK (1 << CL_SD_CTL_IOCE_SHIFT)
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#define CL_SD_CTL_IOCE(x) \
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((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)
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/* FIFO Error Interrupt Enable */
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#define CL_SD_CTL_FEIE_SHIFT 3
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#define CL_SD_CTL_FEIE_MASK (1 << CL_SD_CTL_FEIE_SHIFT)
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#define CL_SD_CTL_FEIE(x) \
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((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)
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/* Descriptor Error Interrupt Enable */
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#define CL_SD_CTL_DEIE_SHIFT 4
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#define CL_SD_CTL_DEIE_MASK (1 << CL_SD_CTL_DEIE_SHIFT)
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#define CL_SD_CTL_DEIE(x) \
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((x << CL_SD_CTL_DEIE_SHIFT) & CL_SD_CTL_DEIE_MASK)
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/* FIFO Limit Change */
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#define CL_SD_CTL_FIFOLC_SHIFT 5
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#define CL_SD_CTL_FIFOLC_MASK (1 << CL_SD_CTL_FIFOLC_SHIFT)
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#define CL_SD_CTL_FIFOLC(x) \
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((x << CL_SD_CTL_FIFOLC_SHIFT) & CL_SD_CTL_FIFOLC_MASK)
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/* Stripe Control */
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#define CL_SD_CTL_STRIPE_SHIFT 16
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#define CL_SD_CTL_STRIPE_MASK (0x3 << CL_SD_CTL_STRIPE_SHIFT)
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#define CL_SD_CTL_STRIPE(x) \
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((x << CL_SD_CTL_STRIPE_SHIFT) & CL_SD_CTL_STRIPE_MASK)
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/* Traffic Priority */
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#define CL_SD_CTL_TP_SHIFT 18
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#define CL_SD_CTL_TP_MASK (1 << CL_SD_CTL_TP_SHIFT)
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#define CL_SD_CTL_TP(x) \
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((x << CL_SD_CTL_TP_SHIFT) & CL_SD_CTL_TP_MASK)
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/* Bidirectional Direction Control */
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#define CL_SD_CTL_DIR_SHIFT 19
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#define CL_SD_CTL_DIR_MASK (1 << CL_SD_CTL_DIR_SHIFT)
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#define CL_SD_CTL_DIR(x) \
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((x << CL_SD_CTL_DIR_SHIFT) & CL_SD_CTL_DIR_MASK)
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/* Stream Number */
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#define CL_SD_CTL_STRM_SHIFT 20
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#define CL_SD_CTL_STRM_MASK (0xf << CL_SD_CTL_STRM_SHIFT)
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#define CL_SD_CTL_STRM(x) \
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((x << CL_SD_CTL_STRM_SHIFT) & CL_SD_CTL_STRM_MASK)
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/* CL: Stream Descriptor x Status */
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/* Buffer Completion Interrupt Status */
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#define CL_SD_STS_BCIS(x) CL_SD_CTL_IOCE(x)
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/* FIFO Error */
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#define CL_SD_STS_FIFOE(x) CL_SD_CTL_FEIE(x)
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/* Descriptor Error */
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#define CL_SD_STS_DESE(x) CL_SD_CTL_DEIE(x)
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/* FIFO Ready */
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#define CL_SD_STS_FIFORDY(x) CL_SD_CTL_FIFOLC(x)
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/* CL: Stream Descriptor x Last Valid Index */
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#define CL_SD_LVI_SHIFT 0
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#define CL_SD_LVI_MASK (0xff << CL_SD_LVI_SHIFT)
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#define CL_SD_LVI(x) ((x << CL_SD_LVI_SHIFT) & CL_SD_LVI_MASK)
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/* CL: Stream Descriptor x FIFO Eviction Watermark */
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#define CL_SD_FIFOW_SHIFT 0
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#define CL_SD_FIFOW_MASK (0x7 << CL_SD_FIFOW_SHIFT)
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#define CL_SD_FIFOW(x) \
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((x << CL_SD_FIFOW_SHIFT) & CL_SD_FIFOW_MASK)
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/* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
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/* Protect Bits */
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#define CL_SD_BDLPLBA_PROT_SHIFT 0
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#define CL_SD_BDLPLBA_PROT_MASK (1 << CL_SD_BDLPLBA_PROT_SHIFT)
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#define CL_SD_BDLPLBA_PROT(x) \
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((x << CL_SD_BDLPLBA_PROT_SHIFT) & CL_SD_BDLPLBA_PROT_MASK)
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/* Buffer Descriptor List Lower Base Address */
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#define CL_SD_BDLPLBA_SHIFT 7
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#define CL_SD_BDLPLBA_MASK (0x1ffffff << CL_SD_BDLPLBA_SHIFT)
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#define CL_SD_BDLPLBA(x) \
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((BDL_ALIGN(lower_32_bits(x)) << CL_SD_BDLPLBA_SHIFT) & CL_SD_BDLPLBA_MASK)
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/* Buffer Descriptor List Upper Base Address */
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#define CL_SD_BDLPUBA_SHIFT 0
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#define CL_SD_BDLPUBA_MASK (0xffffffff << CL_SD_BDLPUBA_SHIFT)
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#define CL_SD_BDLPUBA(x) \
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((upper_32_bits(x) << CL_SD_BDLPUBA_SHIFT) & CL_SD_BDLPUBA_MASK)
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/*
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* Code Loader - Software Position Based FIFO
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* Capability Registers x Software Position Based FIFO Header
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*/
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/* Next Capability Pointer */
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#define CL_SPBFIFO_SPBFCH_PTR_SHIFT 0
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#define CL_SPBFIFO_SPBFCH_PTR_MASK (0xff << CL_SPBFIFO_SPBFCH_PTR_SHIFT)
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#define CL_SPBFIFO_SPBFCH_PTR(x) \
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((x << CL_SPBFIFO_SPBFCH_PTR_SHIFT) & CL_SPBFIFO_SPBFCH_PTR_MASK)
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/* Capability Identifier */
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#define CL_SPBFIFO_SPBFCH_ID_SHIFT 16
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#define CL_SPBFIFO_SPBFCH_ID_MASK (0xfff << CL_SPBFIFO_SPBFCH_ID_SHIFT)
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#define CL_SPBFIFO_SPBFCH_ID(x) \
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((x << CL_SPBFIFO_SPBFCH_ID_SHIFT) & CL_SPBFIFO_SPBFCH_ID_MASK)
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/* Capability Version */
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#define CL_SPBFIFO_SPBFCH_VER_SHIFT 28
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#define CL_SPBFIFO_SPBFCH_VER_MASK (0xf << CL_SPBFIFO_SPBFCH_VER_SHIFT)
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#define CL_SPBFIFO_SPBFCH_VER(x) \
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((x << CL_SPBFIFO_SPBFCH_VER_SHIFT) & CL_SPBFIFO_SPBFCH_VER_MASK)
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/* Software Position in Buffer Enable */
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#define CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT 0
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#define CL_SPBFIFO_SPBFCCTL_SPIBE_MASK (1 << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT)
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#define CL_SPBFIFO_SPBFCCTL_SPIBE(x) \
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((x << CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT) & CL_SPBFIFO_SPBFCCTL_SPIBE_MASK)
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/* SST IPC SKL defines */
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#define SKL_WAIT_TIMEOUT 500 /* 500 msec */
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#define SKL_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
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enum skl_cl_dma_wake_states {
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SKL_CL_DMA_STATUS_NONE = 0,
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SKL_CL_DMA_BUF_COMPLETE,
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SKL_CL_DMA_ERR, /* TODO: Expand the error states */
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};
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struct sst_dsp;
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struct skl_cl_dev_ops {
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void (*cl_setup_bdle)(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_data,
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__le32 **bdlp, int size, int with_ioc);
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void (*cl_setup_controller)(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_bdl,
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unsigned int max_size, u32 page_count);
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void (*cl_setup_spb)(struct sst_dsp *ctx,
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unsigned int size, bool enable);
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void (*cl_cleanup_spb)(struct sst_dsp *ctx);
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void (*cl_trigger)(struct sst_dsp *ctx, bool enable);
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void (*cl_cleanup_controller)(struct sst_dsp *ctx);
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int (*cl_copy_to_dmabuf)(struct sst_dsp *ctx,
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const void *bin, u32 size, bool wait);
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void (*cl_stop_dma)(struct sst_dsp *ctx);
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};
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/**
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* skl_cl_dev - holds information for code loader dma transfer
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*
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* @dmab_data: buffer pointer
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* @dmab_bdl: buffer descriptor list
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* @bufsize: ring buffer size
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* @frags: Last valid buffer descriptor index in the BDL
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* @curr_spib_pos: Current position in ring buffer
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* @dma_buffer_offset: dma buffer offset
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* @ops: operations supported on CL dma
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* @wait_queue: wait queue to wake for wake event
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* @wake_status: DMA wake status
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* @wait_condition: condition to wait on wait queue
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* @cl_dma_lock: for synchronized access to cldma
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*/
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struct skl_cl_dev {
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struct snd_dma_buffer dmab_data;
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struct snd_dma_buffer dmab_bdl;
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unsigned int bufsize;
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unsigned int frags;
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unsigned int curr_spib_pos;
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unsigned int dma_buffer_offset;
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struct skl_cl_dev_ops ops;
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wait_queue_head_t wait_queue;
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int wake_status;
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bool wait_condition;
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};
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#endif /* SKL_SST_CLDMA_H_ */
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