148 lines
4.5 KiB
C
148 lines
4.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __SOUND_WM8766_H
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#define __SOUND_WM8766_H
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/*
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* ALSA driver for ICEnsemble VT17xx
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*
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* Lowlevel functions for WM8766 codec
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*
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* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
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*/
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#define WM8766_REG_DACL1 0x00
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#define WM8766_REG_DACR1 0x01
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#define WM8766_VOL_MASK 0x1ff /* incl. update bit */
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#define WM8766_VOL_UPDATE (1 << 8) /* update volume */
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#define WM8766_REG_DACCTRL1 0x02
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#define WM8766_DAC_MUTEALL (1 << 0)
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#define WM8766_DAC_DEEMPALL (1 << 1)
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#define WM8766_DAC_PDWN (1 << 2)
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#define WM8766_DAC_ATC (1 << 3)
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#define WM8766_DAC_IZD (1 << 4)
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#define WM8766_DAC_PL_MASK 0x1e0
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#define WM8766_DAC_PL_LL (1 << 5) /* L chan: L signal */
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#define WM8766_DAC_PL_LR (2 << 5) /* L chan: R signal */
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#define WM8766_DAC_PL_LB (3 << 5) /* L chan: both */
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#define WM8766_DAC_PL_RL (1 << 7) /* R chan: L signal */
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#define WM8766_DAC_PL_RR (2 << 7) /* R chan: R signal */
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#define WM8766_DAC_PL_RB (3 << 7) /* R chan: both */
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#define WM8766_REG_IFCTRL 0x03
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#define WM8766_IF_FMT_RIGHTJ (0 << 0)
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#define WM8766_IF_FMT_LEFTJ (1 << 0)
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#define WM8766_IF_FMT_I2S (2 << 0)
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#define WM8766_IF_FMT_DSP (3 << 0)
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#define WM8766_IF_DSP_LATE (1 << 2) /* in DSP mode */
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#define WM8766_IF_LRC_INVERTED (1 << 2) /* in other modes */
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#define WM8766_IF_BCLK_INVERTED (1 << 3)
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#define WM8766_IF_IWL_16BIT (0 << 4)
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#define WM8766_IF_IWL_20BIT (1 << 4)
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#define WM8766_IF_IWL_24BIT (2 << 4)
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#define WM8766_IF_IWL_32BIT (3 << 4)
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#define WM8766_IF_MASK 0x3f
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#define WM8766_PHASE_INVERT1 (1 << 6)
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#define WM8766_PHASE_INVERT2 (1 << 7)
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#define WM8766_PHASE_INVERT3 (1 << 8)
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#define WM8766_REG_DACL2 0x04
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#define WM8766_REG_DACR2 0x05
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#define WM8766_REG_DACL3 0x06
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#define WM8766_REG_DACR3 0x07
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#define WM8766_REG_MASTDA 0x08
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#define WM8766_REG_DACCTRL2 0x09
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#define WM8766_DAC2_ZCD (1 << 0)
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#define WM8766_DAC2_ZFLAG_ALL (0 << 1)
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#define WM8766_DAC2_ZFLAG_1 (1 << 1)
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#define WM8766_DAC2_ZFLAG_2 (2 << 1)
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#define WM8766_DAC2_ZFLAG_3 (3 << 1)
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#define WM8766_DAC2_MUTE1 (1 << 3)
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#define WM8766_DAC2_MUTE2 (1 << 4)
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#define WM8766_DAC2_MUTE3 (1 << 5)
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#define WM8766_DAC2_DEEMP1 (1 << 6)
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#define WM8766_DAC2_DEEMP2 (1 << 7)
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#define WM8766_DAC2_DEEMP3 (1 << 8)
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#define WM8766_REG_DACCTRL3 0x0a
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#define WM8766_DAC3_DACPD1 (1 << 1)
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#define WM8766_DAC3_DACPD2 (1 << 2)
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#define WM8766_DAC3_DACPD3 (1 << 3)
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#define WM8766_DAC3_PWRDNALL (1 << 4)
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#define WM8766_DAC3_POWER_MASK 0x1e
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#define WM8766_DAC3_MASTER (1 << 5)
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#define WM8766_DAC3_DAC128FS (0 << 6)
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#define WM8766_DAC3_DAC192FS (1 << 6)
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#define WM8766_DAC3_DAC256FS (2 << 6)
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#define WM8766_DAC3_DAC384FS (3 << 6)
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#define WM8766_DAC3_DAC512FS (4 << 6)
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#define WM8766_DAC3_DAC768FS (5 << 6)
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#define WM8766_DAC3_MSTR_MASK 0x1e0
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#define WM8766_REG_MUTE1 0x0c
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#define WM8766_MUTE1_MPD (1 << 6)
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#define WM8766_REG_MUTE2 0x0f
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#define WM8766_MUTE2_MPD (1 << 5)
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#define WM8766_REG_RESET 0x1f
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#define WM8766_REG_COUNT 0x10 /* don't cache the RESET register */
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struct snd_wm8766;
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struct snd_wm8766_ops {
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void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);
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};
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enum snd_wm8766_ctl_id {
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WM8766_CTL_CH1_VOL,
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WM8766_CTL_CH2_VOL,
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WM8766_CTL_CH3_VOL,
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WM8766_CTL_CH1_SW,
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WM8766_CTL_CH2_SW,
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WM8766_CTL_CH3_SW,
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WM8766_CTL_PHASE1_SW,
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WM8766_CTL_PHASE2_SW,
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WM8766_CTL_PHASE3_SW,
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WM8766_CTL_DEEMPH1_SW,
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WM8766_CTL_DEEMPH2_SW,
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WM8766_CTL_DEEMPH3_SW,
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WM8766_CTL_IZD_SW,
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WM8766_CTL_ZC_SW,
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WM8766_CTL_COUNT,
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};
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#define WM8766_ENUM_MAX 16
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#define WM8766_FLAG_STEREO (1 << 0)
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#define WM8766_FLAG_VOL_UPDATE (1 << 1)
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#define WM8766_FLAG_INVERT (1 << 2)
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#define WM8766_FLAG_LIM (1 << 3)
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#define WM8766_FLAG_ALC (1 << 4)
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struct snd_wm8766_ctl {
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struct snd_kcontrol *kctl;
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const char *name;
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snd_ctl_elem_type_t type;
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const char *const enum_names[WM8766_ENUM_MAX];
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const unsigned int *tlv;
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u16 reg1, reg2, mask1, mask2, min, max, flags;
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void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);
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void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);
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};
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enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };
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struct snd_wm8766 {
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struct snd_card *card;
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struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];
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enum snd_wm8766_agc_mode agc_mode;
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struct snd_wm8766_ops ops;
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u16 regs[WM8766_REG_COUNT]; /* 9-bit registers */
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};
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void snd_wm8766_init(struct snd_wm8766 *wm);
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void snd_wm8766_resume(struct snd_wm8766 *wm);
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void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);
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void snd_wm8766_volume_restore(struct snd_wm8766 *wm);
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int snd_wm8766_build_controls(struct snd_wm8766 *wm);
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#endif /* __SOUND_WM8766_H */
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