112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_SR_H
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#define _CLOCK_BCM_SR_H
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/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
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#define BCM_SR_GENPLL0 0
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#define BCM_SR_GENPLL0_125M_CLK 1
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#define BCM_SR_GENPLL0_SCR_CLK 2
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#define BCM_SR_GENPLL0_250M_CLK 3
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#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
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#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
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#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
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/* GENPLL 1 clock channel ID MHB PCIE NITRO */
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#define BCM_SR_GENPLL1 0
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#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
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#define BCM_SR_GENPLL1_MHB_APB_CLK 2
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/* GENPLL 2 clock channel ID NITRO MHB*/
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#define BCM_SR_GENPLL2 0
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#define BCM_SR_GENPLL2_NIC_CLK 1
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#define BCM_SR_GENPLL2_TS_500_CLK 2
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#define BCM_SR_GENPLL2_125_NITRO_CLK 3
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#define BCM_SR_GENPLL2_CHIMP_CLK 4
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#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
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#define BCM_SR_GENPLL2_FS4_CLK 6
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/* GENPLL 3 HSLS clock channel ID */
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#define BCM_SR_GENPLL3 0
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#define BCM_SR_GENPLL3_HSLS_CLK 1
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#define BCM_SR_GENPLL3_SDIO_CLK 2
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/* GENPLL 4 SCR clock channel ID */
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#define BCM_SR_GENPLL4 0
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#define BCM_SR_GENPLL4_CCN_CLK 1
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#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
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#define BCM_SR_GENPLL4_NOC_CLK 3
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#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
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#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
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/* GENPLL 5 FS4 clock channel ID */
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#define BCM_SR_GENPLL5 0
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#define BCM_SR_GENPLL5_FS4_HF_CLK 1
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#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
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#define BCM_SR_GENPLL5_RAID_AE_CLK 3
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/* GENPLL 6 NITRO clock channel ID */
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#define BCM_SR_GENPLL6 0
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#define BCM_SR_GENPLL6_48_USB_CLK 1
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/* LCPLL0 clock channel ID */
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#define BCM_SR_LCPLL0 0
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#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
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#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
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#define BCM_SR_LCPLL0_SATA_350_CLK 3
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#define BCM_SR_LCPLL0_SATA_500_CLK 4
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/* LCPLL1 clock channel ID */
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#define BCM_SR_LCPLL1 0
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#define BCM_SR_LCPLL1_WAN_CLK 1
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#define BCM_SR_LCPLL1_USB_REF_CLK 2
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#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
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/* LCPLL PCIE clock channel ID */
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#define BCM_SR_LCPLL_PCIE 0
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#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL0 0
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#define BCM_SR_EMEMPLL0_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL1 0
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#define BCM_SR_EMEMPLL1_EMEM_CLK 1
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/* GENPLL EMEM0 clock channel ID */
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#define BCM_SR_EMEMPLL2 0
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#define BCM_SR_EMEMPLL2_EMEM_CLK 1
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#endif /* _CLOCK_BCM_SR_H */
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