525 lines
12 KiB
C
525 lines
12 KiB
C
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/*
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* Driver for the ST Microelectronics SPEAr3xx pinmux
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <vireshk@kernel.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-spear3xx.h"
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/* pins */
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static const struct pinctrl_pin_desc spear3xx_pins[] = {
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SPEAR_PIN_0_TO_101,
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};
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/* firda_pins */
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static const unsigned firda_pins[] = { 0, 1 };
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static struct spear_muxreg firda_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_FIRDA_MASK,
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.val = PMX_FIRDA_MASK,
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},
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};
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static struct spear_modemux firda_modemux[] = {
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{
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.modes = ~0,
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.muxregs = firda_muxreg,
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.nmuxregs = ARRAY_SIZE(firda_muxreg),
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},
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};
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struct spear_pingroup spear3xx_firda_pingroup = {
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.name = "firda_grp",
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.pins = firda_pins,
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.npins = ARRAY_SIZE(firda_pins),
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.modemuxs = firda_modemux,
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.nmodemuxs = ARRAY_SIZE(firda_modemux),
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};
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static const char *const firda_grps[] = { "firda_grp" };
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struct spear_function spear3xx_firda_function = {
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.name = "firda",
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.groups = firda_grps,
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.ngroups = ARRAY_SIZE(firda_grps),
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};
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/* i2c_pins */
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static const unsigned i2c_pins[] = { 4, 5 };
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static struct spear_muxreg i2c_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_I2C_MASK,
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.val = PMX_I2C_MASK,
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},
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};
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static struct spear_modemux i2c_modemux[] = {
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{
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.modes = ~0,
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.muxregs = i2c_muxreg,
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.nmuxregs = ARRAY_SIZE(i2c_muxreg),
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},
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};
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struct spear_pingroup spear3xx_i2c_pingroup = {
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.name = "i2c0_grp",
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.pins = i2c_pins,
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.npins = ARRAY_SIZE(i2c_pins),
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.modemuxs = i2c_modemux,
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.nmodemuxs = ARRAY_SIZE(i2c_modemux),
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};
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static const char *const i2c_grps[] = { "i2c0_grp" };
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struct spear_function spear3xx_i2c_function = {
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.name = "i2c0",
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.groups = i2c_grps,
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.ngroups = ARRAY_SIZE(i2c_grps),
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};
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/* ssp_cs_pins */
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static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
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static struct spear_muxreg ssp_cs_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_SSP_CS_MASK,
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.val = PMX_SSP_CS_MASK,
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},
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};
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static struct spear_modemux ssp_cs_modemux[] = {
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{
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.modes = ~0,
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.muxregs = ssp_cs_muxreg,
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.nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
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},
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};
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struct spear_pingroup spear3xx_ssp_cs_pingroup = {
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.name = "ssp_cs_grp",
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.pins = ssp_cs_pins,
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.npins = ARRAY_SIZE(ssp_cs_pins),
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.modemuxs = ssp_cs_modemux,
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.nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
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};
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static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
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struct spear_function spear3xx_ssp_cs_function = {
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.name = "ssp_cs",
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.groups = ssp_cs_grps,
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.ngroups = ARRAY_SIZE(ssp_cs_grps),
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};
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/* ssp_pins */
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static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
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static struct spear_muxreg ssp_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_SSP_MASK,
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.val = PMX_SSP_MASK,
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},
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};
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static struct spear_modemux ssp_modemux[] = {
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{
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.modes = ~0,
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.muxregs = ssp_muxreg,
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.nmuxregs = ARRAY_SIZE(ssp_muxreg),
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},
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};
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struct spear_pingroup spear3xx_ssp_pingroup = {
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.name = "ssp0_grp",
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.pins = ssp_pins,
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.npins = ARRAY_SIZE(ssp_pins),
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.modemuxs = ssp_modemux,
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.nmodemuxs = ARRAY_SIZE(ssp_modemux),
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};
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static const char *const ssp_grps[] = { "ssp0_grp" };
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struct spear_function spear3xx_ssp_function = {
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.name = "ssp0",
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.groups = ssp_grps,
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.ngroups = ARRAY_SIZE(ssp_grps),
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};
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/* mii_pins */
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static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
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21, 22, 23, 24, 25, 26, 27 };
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static struct spear_muxreg mii_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_MII_MASK,
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.val = PMX_MII_MASK,
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},
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};
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static struct spear_modemux mii_modemux[] = {
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{
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.modes = ~0,
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.muxregs = mii_muxreg,
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.nmuxregs = ARRAY_SIZE(mii_muxreg),
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},
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};
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struct spear_pingroup spear3xx_mii_pingroup = {
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.name = "mii0_grp",
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.pins = mii_pins,
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.npins = ARRAY_SIZE(mii_pins),
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.modemuxs = mii_modemux,
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.nmodemuxs = ARRAY_SIZE(mii_modemux),
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};
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static const char *const mii_grps[] = { "mii0_grp" };
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struct spear_function spear3xx_mii_function = {
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.name = "mii0",
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.groups = mii_grps,
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.ngroups = ARRAY_SIZE(mii_grps),
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};
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/* gpio0_pin0_pins */
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static const unsigned gpio0_pin0_pins[] = { 28 };
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static struct spear_muxreg gpio0_pin0_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN0_MASK,
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.val = PMX_GPIO_PIN0_MASK,
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},
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};
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static struct spear_modemux gpio0_pin0_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin0_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
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.name = "gpio0_pin0_grp",
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.pins = gpio0_pin0_pins,
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.npins = ARRAY_SIZE(gpio0_pin0_pins),
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.modemuxs = gpio0_pin0_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
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};
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/* gpio0_pin1_pins */
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static const unsigned gpio0_pin1_pins[] = { 29 };
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static struct spear_muxreg gpio0_pin1_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN1_MASK,
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.val = PMX_GPIO_PIN1_MASK,
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},
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};
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static struct spear_modemux gpio0_pin1_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin1_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
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.name = "gpio0_pin1_grp",
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.pins = gpio0_pin1_pins,
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.npins = ARRAY_SIZE(gpio0_pin1_pins),
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.modemuxs = gpio0_pin1_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
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};
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/* gpio0_pin2_pins */
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static const unsigned gpio0_pin2_pins[] = { 30 };
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static struct spear_muxreg gpio0_pin2_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN2_MASK,
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.val = PMX_GPIO_PIN2_MASK,
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},
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};
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static struct spear_modemux gpio0_pin2_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin2_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
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.name = "gpio0_pin2_grp",
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.pins = gpio0_pin2_pins,
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.npins = ARRAY_SIZE(gpio0_pin2_pins),
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.modemuxs = gpio0_pin2_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
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};
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/* gpio0_pin3_pins */
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static const unsigned gpio0_pin3_pins[] = { 31 };
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static struct spear_muxreg gpio0_pin3_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN3_MASK,
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.val = PMX_GPIO_PIN3_MASK,
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},
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};
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static struct spear_modemux gpio0_pin3_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin3_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
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.name = "gpio0_pin3_grp",
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.pins = gpio0_pin3_pins,
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.npins = ARRAY_SIZE(gpio0_pin3_pins),
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.modemuxs = gpio0_pin3_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
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};
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/* gpio0_pin4_pins */
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static const unsigned gpio0_pin4_pins[] = { 32 };
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static struct spear_muxreg gpio0_pin4_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN4_MASK,
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.val = PMX_GPIO_PIN4_MASK,
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},
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};
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static struct spear_modemux gpio0_pin4_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin4_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
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.name = "gpio0_pin4_grp",
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.pins = gpio0_pin4_pins,
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.npins = ARRAY_SIZE(gpio0_pin4_pins),
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.modemuxs = gpio0_pin4_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
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};
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/* gpio0_pin5_pins */
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static const unsigned gpio0_pin5_pins[] = { 33 };
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static struct spear_muxreg gpio0_pin5_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_GPIO_PIN5_MASK,
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.val = PMX_GPIO_PIN5_MASK,
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},
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};
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static struct spear_modemux gpio0_pin5_modemux[] = {
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{
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.modes = ~0,
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.muxregs = gpio0_pin5_muxreg,
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.nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
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},
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};
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struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
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.name = "gpio0_pin5_grp",
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.pins = gpio0_pin5_pins,
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.npins = ARRAY_SIZE(gpio0_pin5_pins),
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.modemuxs = gpio0_pin5_modemux,
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.nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
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};
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static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
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"gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
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};
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struct spear_function spear3xx_gpio0_function = {
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.name = "gpio0",
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.groups = gpio0_grps,
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.ngroups = ARRAY_SIZE(gpio0_grps),
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};
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/* uart0_ext_pins */
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static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
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static struct spear_muxreg uart0_ext_muxreg[] = {
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{
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.reg = -1,
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.mask = PMX_UART0_MODEM_MASK,
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.val = PMX_UART0_MODEM_MASK,
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||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct spear_modemux uart0_ext_modemux[] = {
|
||
|
|
{
|
||
|
|
.modes = ~0,
|
||
|
|
.muxregs = uart0_ext_muxreg,
|
||
|
|
.nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct spear_pingroup spear3xx_uart0_ext_pingroup = {
|
||
|
|
.name = "uart0_ext_grp",
|
||
|
|
.pins = uart0_ext_pins,
|
||
|
|
.npins = ARRAY_SIZE(uart0_ext_pins),
|
||
|
|
.modemuxs = uart0_ext_modemux,
|
||
|
|
.nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
|
||
|
|
struct spear_function spear3xx_uart0_ext_function = {
|
||
|
|
.name = "uart0_ext",
|
||
|
|
.groups = uart0_ext_grps,
|
||
|
|
.ngroups = ARRAY_SIZE(uart0_ext_grps),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* uart0_pins */
|
||
|
|
static const unsigned uart0_pins[] = { 2, 3 };
|
||
|
|
static struct spear_muxreg uart0_muxreg[] = {
|
||
|
|
{
|
||
|
|
.reg = -1,
|
||
|
|
.mask = PMX_UART0_MASK,
|
||
|
|
.val = PMX_UART0_MASK,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct spear_modemux uart0_modemux[] = {
|
||
|
|
{
|
||
|
|
.modes = ~0,
|
||
|
|
.muxregs = uart0_muxreg,
|
||
|
|
.nmuxregs = ARRAY_SIZE(uart0_muxreg),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct spear_pingroup spear3xx_uart0_pingroup = {
|
||
|
|
.name = "uart0_grp",
|
||
|
|
.pins = uart0_pins,
|
||
|
|
.npins = ARRAY_SIZE(uart0_pins),
|
||
|
|
.modemuxs = uart0_modemux,
|
||
|
|
.nmodemuxs = ARRAY_SIZE(uart0_modemux),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const char *const uart0_grps[] = { "uart0_grp" };
|
||
|
|
struct spear_function spear3xx_uart0_function = {
|
||
|
|
.name = "uart0",
|
||
|
|
.groups = uart0_grps,
|
||
|
|
.ngroups = ARRAY_SIZE(uart0_grps),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* timer_0_1_pins */
|
||
|
|
static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
|
||
|
|
static struct spear_muxreg timer_0_1_muxreg[] = {
|
||
|
|
{
|
||
|
|
.reg = -1,
|
||
|
|
.mask = PMX_TIMER_0_1_MASK,
|
||
|
|
.val = PMX_TIMER_0_1_MASK,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct spear_modemux timer_0_1_modemux[] = {
|
||
|
|
{
|
||
|
|
.modes = ~0,
|
||
|
|
.muxregs = timer_0_1_muxreg,
|
||
|
|
.nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct spear_pingroup spear3xx_timer_0_1_pingroup = {
|
||
|
|
.name = "timer_0_1_grp",
|
||
|
|
.pins = timer_0_1_pins,
|
||
|
|
.npins = ARRAY_SIZE(timer_0_1_pins),
|
||
|
|
.modemuxs = timer_0_1_modemux,
|
||
|
|
.nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
|
||
|
|
struct spear_function spear3xx_timer_0_1_function = {
|
||
|
|
.name = "timer_0_1",
|
||
|
|
.groups = timer_0_1_grps,
|
||
|
|
.ngroups = ARRAY_SIZE(timer_0_1_grps),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* timer_2_3_pins */
|
||
|
|
static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
|
||
|
|
static struct spear_muxreg timer_2_3_muxreg[] = {
|
||
|
|
{
|
||
|
|
.reg = -1,
|
||
|
|
.mask = PMX_TIMER_2_3_MASK,
|
||
|
|
.val = PMX_TIMER_2_3_MASK,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct spear_modemux timer_2_3_modemux[] = {
|
||
|
|
{
|
||
|
|
.modes = ~0,
|
||
|
|
.muxregs = timer_2_3_muxreg,
|
||
|
|
.nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
struct spear_pingroup spear3xx_timer_2_3_pingroup = {
|
||
|
|
.name = "timer_2_3_grp",
|
||
|
|
.pins = timer_2_3_pins,
|
||
|
|
.npins = ARRAY_SIZE(timer_2_3_pins),
|
||
|
|
.modemuxs = timer_2_3_modemux,
|
||
|
|
.nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
|
||
|
|
struct spear_function spear3xx_timer_2_3_function = {
|
||
|
|
.name = "timer_2_3",
|
||
|
|
.groups = timer_2_3_grps,
|
||
|
|
.ngroups = ARRAY_SIZE(timer_2_3_grps),
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Define muxreg arrays */
|
||
|
|
DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
|
||
|
|
DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
|
||
|
|
DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
|
||
|
|
DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
|
||
|
|
DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
|
||
|
|
DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
|
||
|
|
DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
|
||
|
|
DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
|
||
|
|
DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
|
||
|
|
DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
|
||
|
|
|
||
|
|
static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
|
||
|
|
GPIO_PINGROUP(firda_pins),
|
||
|
|
GPIO_PINGROUP(i2c_pins),
|
||
|
|
GPIO_PINGROUP(ssp_cs_pins),
|
||
|
|
GPIO_PINGROUP(ssp_pins),
|
||
|
|
GPIO_PINGROUP(mii_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin0_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin1_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin2_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin3_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin4_pins),
|
||
|
|
GPIO_PINGROUP(gpio0_pin5_pins),
|
||
|
|
GPIO_PINGROUP(uart0_ext_pins),
|
||
|
|
GPIO_PINGROUP(uart0_pins),
|
||
|
|
GPIO_PINGROUP(timer_0_1_pins),
|
||
|
|
GPIO_PINGROUP(timer_2_3_pins),
|
||
|
|
};
|
||
|
|
|
||
|
|
struct spear_pinctrl_machdata spear3xx_machdata = {
|
||
|
|
.pins = spear3xx_pins,
|
||
|
|
.npins = ARRAY_SIZE(spear3xx_pins),
|
||
|
|
.gpio_pingroups = spear3xx_gpio_pingroup,
|
||
|
|
.ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
|
||
|
|
};
|