513 lines
16 KiB
C
513 lines
16 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2013 Solarflare Communications Inc.
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*/
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#ifndef EF4_NIC_H
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#define EF4_NIC_H
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#include <linux/net_tstamp.h>
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#include <linux/i2c-algo-bit.h>
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#include "net_driver.h"
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#include "efx.h"
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enum {
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EF4_REV_FALCON_A0 = 0,
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EF4_REV_FALCON_A1 = 1,
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EF4_REV_FALCON_B0 = 2,
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};
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static inline int ef4_nic_rev(struct ef4_nic *efx)
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{
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return efx->type->revision;
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}
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u32 ef4_farch_fpga_ver(struct ef4_nic *efx);
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/* NIC has two interlinked PCI functions for the same port. */
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static inline bool ef4_nic_is_dual_func(struct ef4_nic *efx)
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{
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return ef4_nic_rev(efx) < EF4_REV_FALCON_B0;
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}
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/* Read the current event from the event queue */
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static inline ef4_qword_t *ef4_event(struct ef4_channel *channel,
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unsigned int index)
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{
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return ((ef4_qword_t *) (channel->eventq.buf.addr)) +
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(index & channel->eventq_mask);
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}
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/* See if an event is present
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*
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* We check both the high and low dword of the event for all ones. We
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* wrote all ones when we cleared the event, and no valid event can
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* have all ones in either its high or low dwords. This approach is
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* robust against reordering.
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*
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* Note that using a single 64-bit comparison is incorrect; even
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* though the CPU read will be atomic, the DMA write may not be.
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*/
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static inline int ef4_event_present(ef4_qword_t *event)
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{
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return !(EF4_DWORD_IS_ALL_ONES(event->dword[0]) |
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EF4_DWORD_IS_ALL_ONES(event->dword[1]));
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}
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/* Returns a pointer to the specified transmit descriptor in the TX
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* descriptor queue belonging to the specified channel.
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*/
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static inline ef4_qword_t *
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ef4_tx_desc(struct ef4_tx_queue *tx_queue, unsigned int index)
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{
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return ((ef4_qword_t *) (tx_queue->txd.buf.addr)) + index;
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}
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/* Get partner of a TX queue, seen as part of the same net core queue */
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static inline struct ef4_tx_queue *ef4_tx_queue_partner(struct ef4_tx_queue *tx_queue)
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{
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if (tx_queue->queue & EF4_TXQ_TYPE_OFFLOAD)
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return tx_queue - EF4_TXQ_TYPE_OFFLOAD;
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else
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return tx_queue + EF4_TXQ_TYPE_OFFLOAD;
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}
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/* Report whether this TX queue would be empty for the given write_count.
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* May return false negative.
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*/
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static inline bool __ef4_nic_tx_is_empty(struct ef4_tx_queue *tx_queue,
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unsigned int write_count)
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{
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unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
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if (empty_read_count == 0)
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return false;
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return ((empty_read_count ^ write_count) & ~EF4_EMPTY_COUNT_VALID) == 0;
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}
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/* Decide whether to push a TX descriptor to the NIC vs merely writing
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* the doorbell. This can reduce latency when we are adding a single
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* descriptor to an empty queue, but is otherwise pointless. Further,
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* Falcon and Siena have hardware bugs (SF bug 33851) that may be
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* triggered if we don't check this.
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* We use the write_count used for the last doorbell push, to get the
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* NIC's view of the tx queue.
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*/
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static inline bool ef4_nic_may_push_tx_desc(struct ef4_tx_queue *tx_queue,
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unsigned int write_count)
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{
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bool was_empty = __ef4_nic_tx_is_empty(tx_queue, write_count);
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tx_queue->empty_read_count = 0;
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return was_empty && tx_queue->write_count - write_count == 1;
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}
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/* Returns a pointer to the specified descriptor in the RX descriptor queue */
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static inline ef4_qword_t *
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ef4_rx_desc(struct ef4_rx_queue *rx_queue, unsigned int index)
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{
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return ((ef4_qword_t *) (rx_queue->rxd.buf.addr)) + index;
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}
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enum {
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PHY_TYPE_NONE = 0,
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PHY_TYPE_TXC43128 = 1,
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PHY_TYPE_88E1111 = 2,
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PHY_TYPE_SFX7101 = 3,
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PHY_TYPE_QT2022C2 = 4,
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PHY_TYPE_PM8358 = 6,
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PHY_TYPE_SFT9001A = 8,
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PHY_TYPE_QT2025C = 9,
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PHY_TYPE_SFT9001B = 10,
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};
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#define FALCON_XMAC_LOOPBACKS \
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((1 << LOOPBACK_XGMII) | \
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(1 << LOOPBACK_XGXS) | \
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(1 << LOOPBACK_XAUI))
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/* Alignment of PCIe DMA boundaries (4KB) */
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#define EF4_PAGE_SIZE 4096
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/* Size and alignment of buffer table entries (same) */
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#define EF4_BUF_SIZE EF4_PAGE_SIZE
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/* NIC-generic software stats */
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enum {
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GENERIC_STAT_rx_noskb_drops,
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GENERIC_STAT_rx_nodesc_trunc,
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GENERIC_STAT_COUNT
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};
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/**
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* struct falcon_board_type - board operations and type information
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* @id: Board type id, as found in NVRAM
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* @init: Allocate resources and initialise peripheral hardware
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* @init_phy: Do board-specific PHY initialisation
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* @fini: Shut down hardware and free resources
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* @set_id_led: Set state of identifying LED or revert to automatic function
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* @monitor: Board-specific health check function
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*/
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struct falcon_board_type {
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u8 id;
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int (*init) (struct ef4_nic *nic);
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void (*init_phy) (struct ef4_nic *efx);
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void (*fini) (struct ef4_nic *nic);
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void (*set_id_led) (struct ef4_nic *efx, enum ef4_led_mode mode);
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int (*monitor) (struct ef4_nic *nic);
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};
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/**
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* struct falcon_board - board information
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* @type: Type of board
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* @major: Major rev. ('A', 'B' ...)
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* @minor: Minor rev. (0, 1, ...)
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* @i2c_adap: I2C adapter for on-board peripherals
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* @i2c_data: Data for bit-banging algorithm
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* @hwmon_client: I2C client for hardware monitor
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* @ioexp_client: I2C client for power/port control
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*/
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struct falcon_board {
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const struct falcon_board_type *type;
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int major;
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int minor;
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struct i2c_adapter i2c_adap;
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struct i2c_algo_bit_data i2c_data;
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struct i2c_client *hwmon_client, *ioexp_client;
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};
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/**
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* struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
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* @device_id: Controller's id for the device
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* @size: Size (in bytes)
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* @addr_len: Number of address bytes in read/write commands
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* @munge_address: Flag whether addresses should be munged.
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* Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
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* use bit 3 of the command byte as address bit A8, rather
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* than having a two-byte address. If this flag is set, then
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* commands should be munged in this way.
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* @erase_command: Erase command (or 0 if sector erase not needed).
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* @erase_size: Erase sector size (in bytes)
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* Erase commands affect sectors with this size and alignment.
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* This must be a power of two.
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* @block_size: Write block size (in bytes).
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* Write commands are limited to blocks with this size and alignment.
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*/
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struct falcon_spi_device {
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int device_id;
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unsigned int size;
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unsigned int addr_len;
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unsigned int munge_address:1;
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u8 erase_command;
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unsigned int erase_size;
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unsigned int block_size;
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};
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static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
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{
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return spi->size != 0;
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}
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enum {
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FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT,
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FALCON_STAT_tx_packets,
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FALCON_STAT_tx_pause,
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FALCON_STAT_tx_control,
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FALCON_STAT_tx_unicast,
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FALCON_STAT_tx_multicast,
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FALCON_STAT_tx_broadcast,
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FALCON_STAT_tx_lt64,
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FALCON_STAT_tx_64,
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FALCON_STAT_tx_65_to_127,
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FALCON_STAT_tx_128_to_255,
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FALCON_STAT_tx_256_to_511,
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FALCON_STAT_tx_512_to_1023,
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FALCON_STAT_tx_1024_to_15xx,
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FALCON_STAT_tx_15xx_to_jumbo,
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FALCON_STAT_tx_gtjumbo,
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FALCON_STAT_tx_non_tcpudp,
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FALCON_STAT_tx_mac_src_error,
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FALCON_STAT_tx_ip_src_error,
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FALCON_STAT_rx_bytes,
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FALCON_STAT_rx_good_bytes,
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FALCON_STAT_rx_bad_bytes,
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FALCON_STAT_rx_packets,
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FALCON_STAT_rx_good,
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FALCON_STAT_rx_bad,
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FALCON_STAT_rx_pause,
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FALCON_STAT_rx_control,
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FALCON_STAT_rx_unicast,
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FALCON_STAT_rx_multicast,
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FALCON_STAT_rx_broadcast,
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FALCON_STAT_rx_lt64,
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FALCON_STAT_rx_64,
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FALCON_STAT_rx_65_to_127,
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FALCON_STAT_rx_128_to_255,
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FALCON_STAT_rx_256_to_511,
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FALCON_STAT_rx_512_to_1023,
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FALCON_STAT_rx_1024_to_15xx,
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FALCON_STAT_rx_15xx_to_jumbo,
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FALCON_STAT_rx_gtjumbo,
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FALCON_STAT_rx_bad_lt64,
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FALCON_STAT_rx_bad_gtjumbo,
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FALCON_STAT_rx_overflow,
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FALCON_STAT_rx_symbol_error,
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FALCON_STAT_rx_align_error,
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FALCON_STAT_rx_length_error,
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FALCON_STAT_rx_internal_error,
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FALCON_STAT_rx_nodesc_drop_cnt,
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FALCON_STAT_COUNT
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};
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/**
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* struct falcon_nic_data - Falcon NIC state
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* @pci_dev2: Secondary function of Falcon A
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* @efx: ef4_nic pointer
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* @board: Board state and functions
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* @stats: Hardware statistics
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* @stats_disable_count: Nest count for disabling statistics fetches
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* @stats_pending: Is there a pending DMA of MAC statistics.
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* @stats_timer: A timer for regularly fetching MAC statistics.
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* @spi_flash: SPI flash device
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* @spi_eeprom: SPI EEPROM device
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* @spi_lock: SPI bus lock
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* @mdio_lock: MDIO bus lock
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* @xmac_poll_required: XMAC link state needs polling
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*/
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struct falcon_nic_data {
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struct pci_dev *pci_dev2;
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struct ef4_nic *efx;
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struct falcon_board board;
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u64 stats[FALCON_STAT_COUNT];
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unsigned int stats_disable_count;
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bool stats_pending;
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struct timer_list stats_timer;
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struct falcon_spi_device spi_flash;
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struct falcon_spi_device spi_eeprom;
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struct mutex spi_lock;
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struct mutex mdio_lock;
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bool xmac_poll_required;
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};
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static inline struct falcon_board *falcon_board(struct ef4_nic *efx)
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{
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struct falcon_nic_data *data = efx->nic_data;
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return &data->board;
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}
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struct ethtool_ts_info;
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extern const struct ef4_nic_type falcon_a1_nic_type;
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extern const struct ef4_nic_type falcon_b0_nic_type;
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/**************************************************************************
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*
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* Externs
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*
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**************************************************************************
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*/
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int falcon_probe_board(struct ef4_nic *efx, u16 revision_info);
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/* TX data path */
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static inline int ef4_nic_probe_tx(struct ef4_tx_queue *tx_queue)
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{
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return tx_queue->efx->type->tx_probe(tx_queue);
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}
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static inline void ef4_nic_init_tx(struct ef4_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_init(tx_queue);
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}
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static inline void ef4_nic_remove_tx(struct ef4_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_remove(tx_queue);
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}
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static inline void ef4_nic_push_buffers(struct ef4_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_write(tx_queue);
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}
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/* RX data path */
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static inline int ef4_nic_probe_rx(struct ef4_rx_queue *rx_queue)
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{
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return rx_queue->efx->type->rx_probe(rx_queue);
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}
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static inline void ef4_nic_init_rx(struct ef4_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_init(rx_queue);
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}
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static inline void ef4_nic_remove_rx(struct ef4_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_remove(rx_queue);
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}
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static inline void ef4_nic_notify_rx_desc(struct ef4_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_write(rx_queue);
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}
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static inline void ef4_nic_generate_fill_event(struct ef4_rx_queue *rx_queue)
|
||
|
|
{
|
||
|
|
rx_queue->efx->type->rx_defer_refill(rx_queue);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Event data path */
|
||
|
|
static inline int ef4_nic_probe_eventq(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
return channel->efx->type->ev_probe(channel);
|
||
|
|
}
|
||
|
|
static inline int ef4_nic_init_eventq(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
return channel->efx->type->ev_init(channel);
|
||
|
|
}
|
||
|
|
static inline void ef4_nic_fini_eventq(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
channel->efx->type->ev_fini(channel);
|
||
|
|
}
|
||
|
|
static inline void ef4_nic_remove_eventq(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
channel->efx->type->ev_remove(channel);
|
||
|
|
}
|
||
|
|
static inline int
|
||
|
|
ef4_nic_process_eventq(struct ef4_channel *channel, int quota)
|
||
|
|
{
|
||
|
|
return channel->efx->type->ev_process(channel, quota);
|
||
|
|
}
|
||
|
|
static inline void ef4_nic_eventq_read_ack(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
channel->efx->type->ev_read_ack(channel);
|
||
|
|
}
|
||
|
|
void ef4_nic_event_test_start(struct ef4_channel *channel);
|
||
|
|
|
||
|
|
/* queue operations */
|
||
|
|
int ef4_farch_tx_probe(struct ef4_tx_queue *tx_queue);
|
||
|
|
void ef4_farch_tx_init(struct ef4_tx_queue *tx_queue);
|
||
|
|
void ef4_farch_tx_fini(struct ef4_tx_queue *tx_queue);
|
||
|
|
void ef4_farch_tx_remove(struct ef4_tx_queue *tx_queue);
|
||
|
|
void ef4_farch_tx_write(struct ef4_tx_queue *tx_queue);
|
||
|
|
unsigned int ef4_farch_tx_limit_len(struct ef4_tx_queue *tx_queue,
|
||
|
|
dma_addr_t dma_addr, unsigned int len);
|
||
|
|
int ef4_farch_rx_probe(struct ef4_rx_queue *rx_queue);
|
||
|
|
void ef4_farch_rx_init(struct ef4_rx_queue *rx_queue);
|
||
|
|
void ef4_farch_rx_fini(struct ef4_rx_queue *rx_queue);
|
||
|
|
void ef4_farch_rx_remove(struct ef4_rx_queue *rx_queue);
|
||
|
|
void ef4_farch_rx_write(struct ef4_rx_queue *rx_queue);
|
||
|
|
void ef4_farch_rx_defer_refill(struct ef4_rx_queue *rx_queue);
|
||
|
|
int ef4_farch_ev_probe(struct ef4_channel *channel);
|
||
|
|
int ef4_farch_ev_init(struct ef4_channel *channel);
|
||
|
|
void ef4_farch_ev_fini(struct ef4_channel *channel);
|
||
|
|
void ef4_farch_ev_remove(struct ef4_channel *channel);
|
||
|
|
int ef4_farch_ev_process(struct ef4_channel *channel, int quota);
|
||
|
|
void ef4_farch_ev_read_ack(struct ef4_channel *channel);
|
||
|
|
void ef4_farch_ev_test_generate(struct ef4_channel *channel);
|
||
|
|
|
||
|
|
/* filter operations */
|
||
|
|
int ef4_farch_filter_table_probe(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_filter_table_restore(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_filter_table_remove(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_filter_update_rx_scatter(struct ef4_nic *efx);
|
||
|
|
s32 ef4_farch_filter_insert(struct ef4_nic *efx, struct ef4_filter_spec *spec,
|
||
|
|
bool replace);
|
||
|
|
int ef4_farch_filter_remove_safe(struct ef4_nic *efx,
|
||
|
|
enum ef4_filter_priority priority,
|
||
|
|
u32 filter_id);
|
||
|
|
int ef4_farch_filter_get_safe(struct ef4_nic *efx,
|
||
|
|
enum ef4_filter_priority priority, u32 filter_id,
|
||
|
|
struct ef4_filter_spec *);
|
||
|
|
int ef4_farch_filter_clear_rx(struct ef4_nic *efx,
|
||
|
|
enum ef4_filter_priority priority);
|
||
|
|
u32 ef4_farch_filter_count_rx_used(struct ef4_nic *efx,
|
||
|
|
enum ef4_filter_priority priority);
|
||
|
|
u32 ef4_farch_filter_get_rx_id_limit(struct ef4_nic *efx);
|
||
|
|
s32 ef4_farch_filter_get_rx_ids(struct ef4_nic *efx,
|
||
|
|
enum ef4_filter_priority priority, u32 *buf,
|
||
|
|
u32 size);
|
||
|
|
#ifdef CONFIG_RFS_ACCEL
|
||
|
|
s32 ef4_farch_filter_rfs_insert(struct ef4_nic *efx,
|
||
|
|
struct ef4_filter_spec *spec);
|
||
|
|
bool ef4_farch_filter_rfs_expire_one(struct ef4_nic *efx, u32 flow_id,
|
||
|
|
unsigned int index);
|
||
|
|
#endif
|
||
|
|
void ef4_farch_filter_sync_rx_mode(struct ef4_nic *efx);
|
||
|
|
|
||
|
|
bool ef4_nic_event_present(struct ef4_channel *channel);
|
||
|
|
|
||
|
|
/* Some statistics are computed as A - B where A and B each increase
|
||
|
|
* linearly with some hardware counter(s) and the counters are read
|
||
|
|
* asynchronously. If the counters contributing to B are always read
|
||
|
|
* after those contributing to A, the computed value may be lower than
|
||
|
|
* the true value by some variable amount, and may decrease between
|
||
|
|
* subsequent computations.
|
||
|
|
*
|
||
|
|
* We should never allow statistics to decrease or to exceed the true
|
||
|
|
* value. Since the computed value will never be greater than the
|
||
|
|
* true value, we can achieve this by only storing the computed value
|
||
|
|
* when it increases.
|
||
|
|
*/
|
||
|
|
static inline void ef4_update_diff_stat(u64 *stat, u64 diff)
|
||
|
|
{
|
||
|
|
if ((s64)(diff - *stat) > 0)
|
||
|
|
*stat = diff;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Interrupts */
|
||
|
|
int ef4_nic_init_interrupt(struct ef4_nic *efx);
|
||
|
|
int ef4_nic_irq_test_start(struct ef4_nic *efx);
|
||
|
|
void ef4_nic_fini_interrupt(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_irq_enable_master(struct ef4_nic *efx);
|
||
|
|
int ef4_farch_irq_test_generate(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_irq_disable_master(struct ef4_nic *efx);
|
||
|
|
irqreturn_t ef4_farch_msi_interrupt(int irq, void *dev_id);
|
||
|
|
irqreturn_t ef4_farch_legacy_interrupt(int irq, void *dev_id);
|
||
|
|
irqreturn_t ef4_farch_fatal_interrupt(struct ef4_nic *efx);
|
||
|
|
|
||
|
|
static inline int ef4_nic_event_test_irq_cpu(struct ef4_channel *channel)
|
||
|
|
{
|
||
|
|
return READ_ONCE(channel->event_test_cpu);
|
||
|
|
}
|
||
|
|
static inline int ef4_nic_irq_test_irq_cpu(struct ef4_nic *efx)
|
||
|
|
{
|
||
|
|
return READ_ONCE(efx->last_irq_cpu);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Global Resources */
|
||
|
|
int ef4_nic_flush_queues(struct ef4_nic *efx);
|
||
|
|
int ef4_farch_fini_dmaq(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_finish_flr(struct ef4_nic *efx);
|
||
|
|
void falcon_start_nic_stats(struct ef4_nic *efx);
|
||
|
|
void falcon_stop_nic_stats(struct ef4_nic *efx);
|
||
|
|
int falcon_reset_xaui(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_dimension_resources(struct ef4_nic *efx, unsigned sram_lim_qw);
|
||
|
|
void ef4_farch_init_common(struct ef4_nic *efx);
|
||
|
|
void ef4_farch_rx_push_indir_table(struct ef4_nic *efx);
|
||
|
|
|
||
|
|
int ef4_nic_alloc_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer,
|
||
|
|
unsigned int len, gfp_t gfp_flags);
|
||
|
|
void ef4_nic_free_buffer(struct ef4_nic *efx, struct ef4_buffer *buffer);
|
||
|
|
|
||
|
|
/* Tests */
|
||
|
|
struct ef4_farch_register_test {
|
||
|
|
unsigned address;
|
||
|
|
ef4_oword_t mask;
|
||
|
|
};
|
||
|
|
int ef4_farch_test_registers(struct ef4_nic *efx,
|
||
|
|
const struct ef4_farch_register_test *regs,
|
||
|
|
size_t n_regs);
|
||
|
|
|
||
|
|
size_t ef4_nic_get_regs_len(struct ef4_nic *efx);
|
||
|
|
void ef4_nic_get_regs(struct ef4_nic *efx, void *buf);
|
||
|
|
|
||
|
|
size_t ef4_nic_describe_stats(const struct ef4_hw_stat_desc *desc, size_t count,
|
||
|
|
const unsigned long *mask, u8 *names);
|
||
|
|
void ef4_nic_update_stats(const struct ef4_hw_stat_desc *desc, size_t count,
|
||
|
|
const unsigned long *mask, u64 *stats,
|
||
|
|
const void *dma_buf, bool accumulate);
|
||
|
|
void ef4_nic_fix_nodesc_drop_stat(struct ef4_nic *efx, u64 *stat);
|
||
|
|
|
||
|
|
#define EF4_MAX_FLUSH_TIME 5000
|
||
|
|
|
||
|
|
void ef4_farch_generate_event(struct ef4_nic *efx, unsigned int evq,
|
||
|
|
ef4_qword_t *event);
|
||
|
|
|
||
|
|
#endif /* EF4_NIC_H */
|