417 lines
13 KiB
C
417 lines
13 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
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/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
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#ifndef _MLXSW_PCI_HW_H
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#define _MLXSW_PCI_HW_H
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#include <linux/bitops.h>
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#include "item.h"
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#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
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#define MLXSW_PCI_PAGE_SIZE 4096
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#define MLXSW_PCI_CIR_BASE 0x71000
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#define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
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#define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
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#define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
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#define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
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#define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
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#define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
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#define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
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#define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
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#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
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#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
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#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
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#define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
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#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000
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#define MLXSW_PCI_SW_RESET_WAIT_MSECS 400
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#define MLXSW_PCI_FW_READY 0xA1844
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#define MLXSW_PCI_FW_READY_MASK 0xFFFF
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#define MLXSW_PCI_FW_READY_MAGIC 0x5E
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#define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
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#define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
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#define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
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#define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
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#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
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#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
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#define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
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((offset) + (type_offset) + (num) * 4)
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#define MLXSW_PCI_CQS_MAX 96
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#define MLXSW_PCI_EQS_COUNT 2
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#define MLXSW_PCI_EQ_ASYNC_NUM 0
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#define MLXSW_PCI_EQ_COMP_NUM 1
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#define MLXSW_PCI_SDQS_MIN 2 /* EMAD and control traffic */
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#define MLXSW_PCI_SDQ_EMAD_INDEX 0
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#define MLXSW_PCI_SDQ_EMAD_TC 0
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#define MLXSW_PCI_SDQ_CTL_TC 3
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#define MLXSW_PCI_AQ_PAGES 8
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#define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
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#define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
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#define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
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#define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE
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#define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
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#define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
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#define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
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#define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
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#define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
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#define MLXSW_PCI_WQE_SG_ENTRIES 3
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#define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
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/* pci_wqe_c
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* If set it indicates that a completion should be reported upon
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* execution of this descriptor.
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*/
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MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
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/* pci_wqe_lp
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* Local Processing, set if packet should be processed by the local
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* switch hardware:
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* For Ethernet EMAD (Direct Route and non Direct Route) -
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* must be set if packet destination is local device
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* For InfiniBand CTL - must be set if packet destination is local device
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* Otherwise it must be clear
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* Local Process packets must not exceed the size of 2K (including payload
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* and headers).
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*/
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MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
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/* pci_wqe_type
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* Packet type.
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*/
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MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
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/* pci_wqe_byte_count
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* Size of i-th scatter/gather entry, 0 if entry is unused.
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*/
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MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
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/* pci_wqe_address
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* Physical address of i-th scatter/gather entry.
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* Gather Entries must be 2Byte aligned.
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*/
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MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
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enum mlxsw_pci_cqe_v {
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MLXSW_PCI_CQE_V0,
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MLXSW_PCI_CQE_V1,
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MLXSW_PCI_CQE_V2,
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};
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#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \
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static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
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{ \
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switch (v) { \
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default: \
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case MLXSW_PCI_CQE_V0: \
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return mlxsw_pci_cqe##v0##_##name##_get(cqe); \
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case MLXSW_PCI_CQE_V1: \
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return mlxsw_pci_cqe##v1##_##name##_get(cqe); \
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case MLXSW_PCI_CQE_V2: \
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return mlxsw_pci_cqe##v2##_##name##_get(cqe); \
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} \
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} \
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static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
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char *cqe, u32 val) \
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{ \
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switch (v) { \
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default: \
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case MLXSW_PCI_CQE_V0: \
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mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \
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break; \
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case MLXSW_PCI_CQE_V1: \
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mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \
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break; \
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case MLXSW_PCI_CQE_V2: \
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mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \
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break; \
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} \
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}
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/* pci_cqe_lag
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* Packet arrives from a port which is a LAG
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*/
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MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
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MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
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mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
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/* pci_cqe_system_port/lag_id
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* When lag=0: System port on which the packet was received
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* When lag=1:
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* bits [15:4] LAG ID on which the packet was received
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* bits [3:0] sub_port on which the packet was received
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*/
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MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
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MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
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MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
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mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
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MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
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MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
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mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
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/* pci_cqe_wqe_counter
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* WQE count of the WQEs completed on the associated dqn
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*/
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MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
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/* pci_cqe_byte_count
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* Byte count of received packets including additional two
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* Reserved Bytes that are append to the end of the frame.
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* Reserved for Send CQE.
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*/
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MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
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#define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
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/* pci_cqe_mirror_cong_high
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* Congestion level in units of 8KB of the egress traffic class of the original
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* packet that does mirroring to the CPU. Value of 0xFFFF means that the
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* congestion level is invalid.
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*/
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MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
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/* pci_cqe_trap_id
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* Trap ID that captured the packet.
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*/
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MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
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/* pci_cqe_crc
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* Length include CRC. Indicates the length field includes
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* the packet's CRC.
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*/
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MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
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MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
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mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
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/* pci_cqe_e
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* CQE with Error.
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*/
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MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
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MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
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mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
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/* pci_cqe_sr
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* 1 - Send Queue
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* 0 - Receive Queue
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*/
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MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
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MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
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mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
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/* pci_cqe_dqn
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* Descriptor Queue (DQ) Number.
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*/
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MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
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MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
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mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
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/* pci_cqe_time_stamp_low
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* Time stamp of the CQE
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* Format according to time_stamp_type:
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* 0: uSec - 1.024uSec (default for devices which do not support
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* time_stamp_type). Only bits 15:0 are valid
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* 1: FRC - Free Running Clock - units of 1nSec
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* 2: UTC - time_stamp[37:30] = Sec
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* - time_stamp[29:0] = nSec
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* 3: Mirror_UTC. UTC time stamp of the original packet that has
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* MIRROR_SESSION traps
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* - time_stamp[37:30] = Sec
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* - time_stamp[29:0] = nSec
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* Formats 0..2 are configured by
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* CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
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* Format 3 is used for MIRROR_SESSION traps
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* Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
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*/
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MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
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#define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
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/* pci_cqe_mirror_tclass
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* The egress traffic class of the original packet that does mirroring to the
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* CPU. Value of 0x1F means that the traffic class is invalid.
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*/
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MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
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/* pci_cqe_tx_lag
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* The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.
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*/
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MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
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/* pci_cqe_tx_lag_subport
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* The port index within the LAG of a packet that is mirrored / sampled to the
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* CPU. Reserved when tx_lag is 0.
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*/
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MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
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#define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
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#define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
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/* pci_cqe_tx_lag_id
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* The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.
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* Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
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* is invalid. Reserved when tx_lag is 0.
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*/
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MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
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/* pci_cqe_tx_system_port
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* The Tx port of the original packet that is mirrored / sampled to the CPU.
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* Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
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* invalid. Reserved when tx_lag is 1.
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*/
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MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
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/* pci_cqe_mirror_cong_low
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* Congestion level in units of 8KB of the egress traffic class of the original
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* packet that does mirroring to the CPU. Value of 0xFFFF means that the
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* congestion level is invalid.
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*/
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MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
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#define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT 13 /* Units of 8KB. */
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static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)
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{
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u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);
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u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);
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return cong_high << 12 | cong_low;
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}
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/* pci_cqe_user_def_val_orig_pkt_len
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* When trap_id is an ACL: User defined value from policy engine action.
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*/
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MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
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/* pci_cqe_mirror_reason
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* Mirror reason.
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*/
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MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
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enum mlxsw_pci_cqe_time_stamp_type {
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MLXSW_PCI_CQE_TIME_STAMP_TYPE_USEC,
|
||
|
|
MLXSW_PCI_CQE_TIME_STAMP_TYPE_FRC,
|
||
|
|
MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC,
|
||
|
|
MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* pci_cqe_time_stamp_type
|
||
|
|
* Time stamp type:
|
||
|
|
* 0: uSec - 1.024uSec (default for devices which do not support
|
||
|
|
* time_stamp_type)
|
||
|
|
* 1: FRC - Free Running Clock - units of 1nSec
|
||
|
|
* 2: UTC
|
||
|
|
* 3: Mirror_UTC. UTC time stamp of the original packet that has
|
||
|
|
* MIRROR_SESSION traps
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
|
||
|
|
|
||
|
|
#define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
|
||
|
|
|
||
|
|
/* pci_cqe_time_stamp_high
|
||
|
|
* Time stamp of the CQE
|
||
|
|
* Format according to time_stamp_type:
|
||
|
|
* 0: uSec - 1.024uSec (default for devices which do not support
|
||
|
|
* time_stamp_type). Only bits 15:0 are valid
|
||
|
|
* 1: FRC - Free Running Clock - units of 1nSec
|
||
|
|
* 2: UTC - time_stamp[37:30] = Sec
|
||
|
|
* - time_stamp[29:0] = nSec
|
||
|
|
* 3: Mirror_UTC. UTC time stamp of the original packet that has
|
||
|
|
* MIRROR_SESSION traps
|
||
|
|
* - time_stamp[37:30] = Sec
|
||
|
|
* - time_stamp[29:0] = nSec
|
||
|
|
* Formats 0..2 are configured by
|
||
|
|
* CONFIG_PROFILE.cqe_time_stamp_type for PTP traps
|
||
|
|
* Format 3 is used for MIRROR_SESSION traps
|
||
|
|
* Note that Spectrum does not reveal FRC, UTC and Mirror_UTC
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
|
||
|
|
|
||
|
|
static inline u64 mlxsw_pci_cqe2_time_stamp_get(const char *cqe)
|
||
|
|
{
|
||
|
|
u64 ts_high = mlxsw_pci_cqe2_time_stamp_high_get(cqe);
|
||
|
|
u64 ts_low = mlxsw_pci_cqe2_time_stamp_low_get(cqe);
|
||
|
|
|
||
|
|
return ts_high << 16 | ts_low;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u8 mlxsw_pci_cqe2_time_stamp_sec_get(const char *cqe)
|
||
|
|
{
|
||
|
|
u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
|
||
|
|
|
||
|
|
return full_ts >> 30 & 0xFF;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 mlxsw_pci_cqe2_time_stamp_nsec_get(const char *cqe)
|
||
|
|
{
|
||
|
|
u64 full_ts = mlxsw_pci_cqe2_time_stamp_get(cqe);
|
||
|
|
|
||
|
|
return full_ts & 0x3FFFFFFF;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* pci_cqe_mirror_latency
|
||
|
|
* End-to-end latency of the original packet that does mirroring to the CPU.
|
||
|
|
* Value of 0xFFFFFF means that the latency is invalid. Units are according to
|
||
|
|
* MOGCR.mirror_latency_units.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
|
||
|
|
|
||
|
|
/* pci_cqe_owner
|
||
|
|
* Ownership bit.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
|
||
|
|
MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
|
||
|
|
mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
|
||
|
|
|
||
|
|
/* pci_eqe_event_type
|
||
|
|
* Event type.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
|
||
|
|
#define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
|
||
|
|
#define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
|
||
|
|
|
||
|
|
/* pci_eqe_event_sub_type
|
||
|
|
* Event type.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
|
||
|
|
|
||
|
|
/* pci_eqe_cqn
|
||
|
|
* Completion Queue that triggered this EQE.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
|
||
|
|
|
||
|
|
/* pci_eqe_owner
|
||
|
|
* Ownership bit.
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
|
||
|
|
|
||
|
|
/* pci_eqe_cmd_token
|
||
|
|
* Command completion event - token
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
|
||
|
|
|
||
|
|
/* pci_eqe_cmd_status
|
||
|
|
* Command completion event - status
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
|
||
|
|
|
||
|
|
/* pci_eqe_cmd_out_param_h
|
||
|
|
* Command completion event - output parameter - higher part
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
|
||
|
|
|
||
|
|
/* pci_eqe_cmd_out_param_l
|
||
|
|
* Command completion event - output parameter - lower part
|
||
|
|
*/
|
||
|
|
MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
|
||
|
|
|
||
|
|
#endif
|