205 lines
6.3 KiB
C
205 lines
6.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell Octeon EP (EndPoint) Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef _OCTEP_CONFIG_H_
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#define _OCTEP_CONFIG_H_
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/* Tx instruction types by length */
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#define OCTEP_32BYTE_INSTR 32
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#define OCTEP_64BYTE_INSTR 64
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/* Tx Queue: maximum descriptors per ring */
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#define OCTEP_IQ_MAX_DESCRIPTORS 1024
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/* Minimum input (Tx) requests to be enqueued to ring doorbell */
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#define OCTEP_DB_MIN 1
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/* Packet threshold for Tx queue interrupt */
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#define OCTEP_IQ_INTR_THRESHOLD 0x0
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/* Rx Queue: maximum descriptors per ring */
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#define OCTEP_OQ_MAX_DESCRIPTORS 1024
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/* Rx buffer size: Use page size buffers.
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* Build skb from allocated page buffer once the packet is received.
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* When a gathered packet is received, make head page as skb head and
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* page buffers in consecutive Rx descriptors as fragments.
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*/
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#define OCTEP_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE))
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#define OCTEP_OQ_PKTS_PER_INTR 128
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#define OCTEP_OQ_REFILL_THRESHOLD (OCTEP_OQ_MAX_DESCRIPTORS / 4)
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#define OCTEP_OQ_INTR_PKT_THRESHOLD 1
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#define OCTEP_OQ_INTR_TIME_THRESHOLD 10
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#define OCTEP_MSIX_NAME_SIZE (IFNAMSIZ + 32)
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/* Tx Queue wake threshold
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* wakeup a stopped Tx queue if minimum 2 descriptors are available.
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* Even a skb with fragments consume only one Tx queue descriptor entry.
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*/
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#define OCTEP_WAKE_QUEUE_THRESHOLD 2
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/* Minimum MTU supported by Octeon network interface */
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#define OCTEP_MIN_MTU ETH_MIN_MTU
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/* Maximum MTU supported by Octeon interface*/
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#define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
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/* Default MTU */
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#define OCTEP_DEFAULT_MTU 1500
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/* Macros to get octeon config params */
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#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
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#define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
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#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
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#define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind)
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#define CFG_GET_IQ_INSTR_SIZE(cfg) (64)
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#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
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#define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
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#define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs)
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#define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size)
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#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
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#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
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#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
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#define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.max_io_rings)
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#define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings)
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#define CFG_GET_PORTS_PF_SRN(cfg) ((cfg)->pf_ring_cfg.srn)
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#define CFG_GET_DPI_PKIND(cfg) ((cfg)->core_cfg.dpi_pkind)
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#define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us)
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#define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us)
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#define CFG_GET_MAX_VFS(cfg) ((cfg)->sriov_cfg.max_vfs)
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#define CFG_GET_ACTIVE_VFS(cfg) ((cfg)->sriov_cfg.active_vfs)
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#define CFG_GET_MAX_RPVF(cfg) ((cfg)->sriov_cfg.max_rings_per_vf)
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#define CFG_GET_ACTIVE_RPVF(cfg) ((cfg)->sriov_cfg.active_rings_per_vf)
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#define CFG_GET_VF_SRN(cfg) ((cfg)->sriov_cfg.vf_srn)
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#define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix)
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#define CFG_GET_NON_IOQ_MSIX(cfg) ((cfg)->msix_cfg.non_ioq_msix)
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#define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) ((cfg)->msix_cfg.non_ioq_msix_names)
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#define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) ((cfg)->ctrl_mbox_cfg.barmem_addr)
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/* Hardware Tx Queue configuration. */
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struct octep_iq_config {
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/* Size of the Input queue (number of commands) */
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u16 num_descs;
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/* Command size - 32 or 64 bytes */
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u16 instr_type;
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/* pkind for packets sent to Octeon */
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u16 pkind;
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/* Minimum number of commands pending to be posted to Octeon before driver
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* hits the Input queue doorbell.
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*/
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u16 db_min;
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/* Trigger the IQ interrupt when processed cmd count reaches
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* this level.
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*/
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u32 intr_threshold;
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};
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/* Hardware Rx Queue configuration. */
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struct octep_oq_config {
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/* Size of Output queue (number of descriptors) */
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u16 num_descs;
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/* Size of buffer in this Output queue. */
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u16 buf_size;
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/* The number of buffers that were consumed during packet processing
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* by the driver on this Output queue before the driver attempts to
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* replenish the descriptor ring with new buffers.
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*/
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u16 refill_threshold;
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/* Interrupt Coalescing (Packet Count). Octeon will interrupt the host
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* only if it sent as many packets as specified by this field.
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* The driver usually does not use packet count interrupt coalescing.
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*/
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u32 oq_intr_pkt;
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/* Interrupt Coalescing (Time Interval). Octeon will interrupt the host
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* if at least one packet was sent in the time interval specified by
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* this field. The driver uses time interval interrupt coalescing by
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* default. The time is specified in microseconds.
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*/
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u32 oq_intr_time;
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};
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/* Tx/Rx configuration */
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struct octep_pf_ring_config {
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/* Max number of IOQs */
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u16 max_io_rings;
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/* Number of active IOQs */
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u16 active_io_rings;
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/* Starting IOQ number: this changes based on which PEM is used */
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u16 srn;
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};
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/* Octeon Hardware SRIOV config */
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struct octep_sriov_config {
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/* Max number of VF devices supported */
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u16 max_vfs;
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/* Number of VF devices enabled */
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u16 active_vfs;
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/* Max number of rings assigned to VF */
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u8 max_rings_per_vf;
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/* Number of rings enabled per VF */
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u8 active_rings_per_vf;
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/* starting ring number of VF's: ring-0 of VF-0 of the PF */
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u16 vf_srn;
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};
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/* Octeon MSI-x config. */
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struct octep_msix_config {
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/* Number of IOQ interrupts */
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u16 ioq_msix;
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/* Number of Non IOQ interrupts */
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u16 non_ioq_msix;
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/* Names of Non IOQ interrupts */
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char **non_ioq_msix_names;
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};
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struct octep_ctrl_mbox_config {
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/* Barmem address for control mbox */
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void __iomem *barmem_addr;
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};
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/* Data Structure to hold configuration limits and active config */
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struct octep_config {
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/* Input Queue attributes. */
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struct octep_iq_config iq;
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/* Output Queue attributes. */
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struct octep_oq_config oq;
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/* NIC Port Configuration */
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struct octep_pf_ring_config pf_ring_cfg;
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/* SRIOV configuration of the PF */
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struct octep_sriov_config sriov_cfg;
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/* MSI-X interrupt config */
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struct octep_msix_config msix_cfg;
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/* ctrl mbox config */
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struct octep_ctrl_mbox_config ctrl_mbox_cfg;
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};
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#endif /* _OCTEP_CONFIG_H_ */
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