193 lines
6.0 KiB
C
193 lines
6.0 KiB
C
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/*
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* Driver for Marvell NETA network controller Buffer Manager.
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*
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* Copyright (C) 2015 Marvell
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*
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* Marcin Wojtas <mw@semihalf.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef _MVNETA_BM_H_
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#define _MVNETA_BM_H_
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/* BM Configuration Register */
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#define MVNETA_BM_CONFIG_REG 0x0
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#define MVNETA_BM_STATUS_MASK 0x30
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#define MVNETA_BM_ACTIVE_MASK BIT(4)
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#define MVNETA_BM_MAX_IN_BURST_SIZE_MASK 0x60000
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#define MVNETA_BM_MAX_IN_BURST_SIZE_16BP BIT(18)
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#define MVNETA_BM_EMPTY_LIMIT_MASK BIT(19)
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/* BM Activation Register */
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#define MVNETA_BM_COMMAND_REG 0x4
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#define MVNETA_BM_START_MASK BIT(0)
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#define MVNETA_BM_STOP_MASK BIT(1)
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#define MVNETA_BM_PAUSE_MASK BIT(2)
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/* BM Xbar interface Register */
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#define MVNETA_BM_XBAR_01_REG 0x8
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#define MVNETA_BM_XBAR_23_REG 0xc
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#define MVNETA_BM_XBAR_POOL_REG(pool) \
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(((pool) < 2) ? MVNETA_BM_XBAR_01_REG : MVNETA_BM_XBAR_23_REG)
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#define MVNETA_BM_TARGET_ID_OFFS(pool) (((pool) & 1) ? 16 : 0)
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#define MVNETA_BM_TARGET_ID_MASK(pool) \
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(0xf << MVNETA_BM_TARGET_ID_OFFS(pool))
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#define MVNETA_BM_TARGET_ID_VAL(pool, id) \
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((id) << MVNETA_BM_TARGET_ID_OFFS(pool))
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#define MVNETA_BM_XBAR_ATTR_OFFS(pool) (((pool) & 1) ? 20 : 4)
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#define MVNETA_BM_XBAR_ATTR_MASK(pool) \
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(0xff << MVNETA_BM_XBAR_ATTR_OFFS(pool))
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#define MVNETA_BM_XBAR_ATTR_VAL(pool, attr) \
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((attr) << MVNETA_BM_XBAR_ATTR_OFFS(pool))
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/* Address of External Buffer Pointers Pool Register */
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#define MVNETA_BM_POOL_BASE_REG(pool) (0x10 + ((pool) << 4))
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#define MVNETA_BM_POOL_ENABLE_MASK BIT(0)
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/* External Buffer Pointers Pool RD pointer Register */
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#define MVNETA_BM_POOL_READ_PTR_REG(pool) (0x14 + ((pool) << 4))
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#define MVNETA_BM_POOL_SET_READ_PTR_MASK 0xfffc
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#define MVNETA_BM_POOL_GET_READ_PTR_OFFS 16
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#define MVNETA_BM_POOL_GET_READ_PTR_MASK 0xfffc0000
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/* External Buffer Pointers Pool WR pointer */
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#define MVNETA_BM_POOL_WRITE_PTR_REG(pool) (0x18 + ((pool) << 4))
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#define MVNETA_BM_POOL_SET_WRITE_PTR_OFFS 0
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#define MVNETA_BM_POOL_SET_WRITE_PTR_MASK 0xfffc
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#define MVNETA_BM_POOL_GET_WRITE_PTR_OFFS 16
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#define MVNETA_BM_POOL_GET_WRITE_PTR_MASK 0xfffc0000
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/* External Buffer Pointers Pool Size Register */
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#define MVNETA_BM_POOL_SIZE_REG(pool) (0x1c + ((pool) << 4))
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#define MVNETA_BM_POOL_SIZE_MASK 0x3fff
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/* BM Interrupt Cause Register */
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#define MVNETA_BM_INTR_CAUSE_REG (0x50)
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/* BM interrupt Mask Register */
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#define MVNETA_BM_INTR_MASK_REG (0x54)
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/* Other definitions */
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#define MVNETA_BM_SHORT_PKT_SIZE 256
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#define MVNETA_BM_POOLS_NUM 4
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#define MVNETA_BM_POOL_CAP_MIN 128
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#define MVNETA_BM_POOL_CAP_DEF 2048
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#define MVNETA_BM_POOL_CAP_MAX \
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(16 * 1024 - MVNETA_BM_POOL_CAP_ALIGN)
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#define MVNETA_BM_POOL_CAP_ALIGN 32
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#define MVNETA_BM_POOL_PTR_ALIGN 32
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#define MVNETA_BM_POOL_ACCESS_OFFS 8
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#define MVNETA_BM_BPPI_SIZE 0x100000
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#define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
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enum mvneta_bm_type {
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MVNETA_BM_FREE,
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MVNETA_BM_LONG,
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MVNETA_BM_SHORT
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};
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struct mvneta_bm {
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void __iomem *reg_base;
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struct clk *clk;
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struct platform_device *pdev;
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struct gen_pool *bppi_pool;
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/* BPPI virtual base address */
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void __iomem *bppi_virt_addr;
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/* BPPI physical base address */
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dma_addr_t bppi_phys_addr;
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/* BM pools */
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struct mvneta_bm_pool *bm_pools;
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};
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struct mvneta_bm_pool {
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struct hwbm_pool hwbm_pool;
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/* Pool number in the range 0-3 */
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u8 id;
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enum mvneta_bm_type type;
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/* Packet size */
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int pkt_size;
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/* Size of the buffer acces through DMA*/
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u32 buf_size;
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/* BPPE virtual base address */
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u32 *virt_addr;
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/* BPPE physical base address */
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dma_addr_t phys_addr;
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/* Ports using BM pool */
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u8 port_map;
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struct mvneta_bm *priv;
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};
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/* Declarations and definitions */
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#if IS_ENABLED(CONFIG_MVNETA_BM)
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struct mvneta_bm *mvneta_bm_get(struct device_node *node);
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void mvneta_bm_put(struct mvneta_bm *priv);
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void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool, u8 port_map);
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void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
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u8 port_map);
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int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf);
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int mvneta_bm_pool_refill(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool);
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struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
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enum mvneta_bm_type type, u8 port_id,
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int pkt_size);
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static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool,
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dma_addr_t buf_phys_addr)
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{
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writel_relaxed(buf_phys_addr, priv->bppi_virt_addr +
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(bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
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}
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static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool)
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{
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return readl_relaxed(priv->bppi_virt_addr +
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(bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
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}
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#else
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static inline void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool,
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u8 port_map) {}
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static inline void mvneta_bm_bufs_free(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool,
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u8 port_map) {}
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static inline int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
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{ return 0; }
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static inline int mvneta_bm_pool_refill(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool)
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{ return 0; }
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static inline struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv,
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u8 pool_id,
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enum mvneta_bm_type type,
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u8 port_id,
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int pkt_size)
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{ return NULL; }
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static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool,
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dma_addr_t buf_phys_addr) {}
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static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool)
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{ return 0; }
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static inline struct mvneta_bm *mvneta_bm_get(struct device_node *node)
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{ return NULL; }
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static inline void mvneta_bm_put(struct mvneta_bm *priv) {}
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#endif /* CONFIG_MVNETA_BM */
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#endif
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