434 lines
11 KiB
C
434 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2016-2019 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "../habanalabs.h"
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#include "../../include/hw_ip/pci/pci_general.h"
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#include <linux/pci.h>
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#define HL_PLDM_PCI_ELBI_TIMEOUT_MSEC (HL_PCI_ELBI_TIMEOUT_MSEC * 100)
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#define IATU_REGION_CTRL_REGION_EN_MASK BIT(31)
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#define IATU_REGION_CTRL_MATCH_MODE_MASK BIT(30)
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#define IATU_REGION_CTRL_NUM_MATCH_EN_MASK BIT(19)
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#define IATU_REGION_CTRL_BAR_NUM_MASK GENMASK(10, 8)
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/**
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* hl_pci_bars_map() - Map PCI BARs.
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* @hdev: Pointer to hl_device structure.
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* @name: Array of BAR names.
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* @is_wc: Array with flag per BAR whether a write-combined mapping is needed.
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*
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* Request PCI regions and map them to kernel virtual addresses.
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*
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* Return: 0 on success, non-zero for failure.
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*/
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int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
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bool is_wc[3])
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{
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struct pci_dev *pdev = hdev->pdev;
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int rc, i, bar;
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rc = pci_request_regions(pdev, HL_NAME);
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if (rc) {
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dev_err(hdev->dev, "Cannot obtain PCI resources\n");
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return rc;
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}
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for (i = 0 ; i < 3 ; i++) {
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bar = i * 2; /* 64-bit BARs */
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hdev->pcie_bar[bar] = is_wc[i] ?
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pci_ioremap_wc_bar(pdev, bar) :
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pci_ioremap_bar(pdev, bar);
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if (!hdev->pcie_bar[bar]) {
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dev_err(hdev->dev, "pci_ioremap%s_bar failed for %s\n",
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is_wc[i] ? "_wc" : "", name[i]);
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rc = -ENODEV;
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goto err;
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}
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}
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return 0;
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err:
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for (i = 2 ; i >= 0 ; i--) {
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bar = i * 2; /* 64-bit BARs */
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if (hdev->pcie_bar[bar])
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iounmap(hdev->pcie_bar[bar]);
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}
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pci_release_regions(pdev);
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return rc;
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}
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/**
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* hl_pci_bars_unmap() - Unmap PCI BARS.
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* @hdev: Pointer to hl_device structure.
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*
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* Release all PCI BARs and unmap their virtual addresses.
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*/
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static void hl_pci_bars_unmap(struct hl_device *hdev)
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{
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struct pci_dev *pdev = hdev->pdev;
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int i, bar;
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for (i = 2 ; i >= 0 ; i--) {
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bar = i * 2; /* 64-bit BARs */
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iounmap(hdev->pcie_bar[bar]);
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}
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pci_release_regions(pdev);
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}
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int hl_pci_elbi_read(struct hl_device *hdev, u64 addr, u32 *data)
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{
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struct pci_dev *pdev = hdev->pdev;
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ktime_t timeout;
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u64 msec;
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u32 val;
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if (hdev->pldm)
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msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
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else
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msec = HL_PCI_ELBI_TIMEOUT_MSEC;
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/* Clear previous status */
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL, 0);
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timeout = ktime_add_ms(ktime_get(), msec);
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for (;;) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
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if (val & PCI_CONFIG_ELBI_STS_MASK)
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break;
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if (ktime_compare(ktime_get(), timeout) > 0) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
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&val);
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break;
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}
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usleep_range(300, 500);
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}
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if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
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return 0;
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}
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if (val & PCI_CONFIG_ELBI_STS_ERR) {
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dev_err(hdev->dev, "Error reading from ELBI\n");
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return -EIO;
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}
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if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
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dev_err(hdev->dev, "ELBI read didn't finish in time\n");
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return -EIO;
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}
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dev_err(hdev->dev, "ELBI read has undefined bits in status\n");
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return -EIO;
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}
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/**
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* hl_pci_elbi_write() - Write through the ELBI interface.
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* @hdev: Pointer to hl_device structure.
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* @addr: Address to write to
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* @data: Data to write
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*
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* Return: 0 on success, negative value for failure.
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*/
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static int hl_pci_elbi_write(struct hl_device *hdev, u64 addr, u32 data)
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{
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struct pci_dev *pdev = hdev->pdev;
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ktime_t timeout;
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u64 msec;
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u32 val;
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if (hdev->pldm)
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msec = HL_PLDM_PCI_ELBI_TIMEOUT_MSEC;
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else
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msec = HL_PCI_ELBI_TIMEOUT_MSEC;
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/* Clear previous status */
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, 0);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_ADDR, (u32) addr);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_DATA, data);
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pci_write_config_dword(pdev, mmPCI_CONFIG_ELBI_CTRL,
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PCI_CONFIG_ELBI_CTRL_WRITE);
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timeout = ktime_add_ms(ktime_get(), msec);
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for (;;) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS, &val);
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if (val & PCI_CONFIG_ELBI_STS_MASK)
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break;
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if (ktime_compare(ktime_get(), timeout) > 0) {
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pci_read_config_dword(pdev, mmPCI_CONFIG_ELBI_STS,
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&val);
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break;
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}
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usleep_range(300, 500);
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}
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if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
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return 0;
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if (val & PCI_CONFIG_ELBI_STS_ERR)
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return -EIO;
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if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
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dev_err(hdev->dev, "ELBI write didn't finish in time\n");
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return -EIO;
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}
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dev_err(hdev->dev, "ELBI write has undefined bits in status\n");
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return -EIO;
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}
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/**
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* hl_pci_iatu_write() - iatu write routine.
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* @hdev: Pointer to hl_device structure.
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* @addr: Address to write to
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* @data: Data to write
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u32 dbi_offset;
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int rc;
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dbi_offset = addr & 0xFFF;
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/* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
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* in case the firmware security is enabled
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*/
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hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
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rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
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data);
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if (rc)
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return -EIO;
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return 0;
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}
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/**
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* hl_pci_set_inbound_region() - Configure inbound region
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* @hdev: Pointer to hl_device structure.
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* @region: Inbound region number.
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* @pci_region: Inbound region parameters.
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*
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* Configure the iATU inbound region.
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
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struct hl_inbound_pci_region *pci_region)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 bar_phys_base, region_base, region_end_address;
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u32 offset, ctrl_reg_val;
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int rc = 0;
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/* region offset */
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offset = (0x200 * region) + 0x100;
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if (pci_region->mode == PCI_ADDRESS_MATCH_MODE) {
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bar_phys_base = hdev->pcie_bar_phys[pci_region->bar];
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region_base = bar_phys_base + pci_region->offset_in_bar;
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region_end_address = region_base + pci_region->size - 1;
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rc |= hl_pci_iatu_write(hdev, offset + 0x8,
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lower_32_bits(region_base));
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rc |= hl_pci_iatu_write(hdev, offset + 0xC,
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upper_32_bits(region_base));
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rc |= hl_pci_iatu_write(hdev, offset + 0x10,
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lower_32_bits(region_end_address));
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}
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/* Point to the specified address */
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rc |= hl_pci_iatu_write(hdev, offset + 0x14, lower_32_bits(pci_region->addr));
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rc |= hl_pci_iatu_write(hdev, offset + 0x18, upper_32_bits(pci_region->addr));
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/* Set bar type as memory */
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rc |= hl_pci_iatu_write(hdev, offset + 0x0, 0);
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/* Enable + bar/address match + match enable + bar number */
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ctrl_reg_val = FIELD_PREP(IATU_REGION_CTRL_REGION_EN_MASK, 1);
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ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_MATCH_MODE_MASK, pci_region->mode);
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ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_NUM_MATCH_EN_MASK, 1);
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if (pci_region->mode == PCI_BAR_MATCH_MODE)
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ctrl_reg_val |= FIELD_PREP(IATU_REGION_CTRL_BAR_NUM_MASK, pci_region->bar);
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rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
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/* Return the DBI window to the default location
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* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
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* in case the firmware security is enabled
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*/
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hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
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if (rc)
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dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
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pci_region->bar, pci_region->addr);
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return rc;
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}
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/**
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* hl_pci_set_outbound_region() - Configure outbound region 0
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* @hdev: Pointer to hl_device structure.
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* @pci_region: Outbound region parameters.
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*
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* Configure the iATU outbound region 0.
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*
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* Return: 0 on success, negative value for failure.
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*/
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int hl_pci_set_outbound_region(struct hl_device *hdev,
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struct hl_outbound_pci_region *pci_region)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 outbound_region_end_address;
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int rc = 0;
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/* Outbound Region 0 */
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outbound_region_end_address =
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pci_region->addr + pci_region->size - 1;
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rc |= hl_pci_iatu_write(hdev, 0x008,
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lower_32_bits(pci_region->addr));
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rc |= hl_pci_iatu_write(hdev, 0x00C,
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upper_32_bits(pci_region->addr));
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rc |= hl_pci_iatu_write(hdev, 0x010,
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lower_32_bits(outbound_region_end_address));
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rc |= hl_pci_iatu_write(hdev, 0x014, 0);
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rc |= hl_pci_iatu_write(hdev, 0x018, 0);
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rc |= hl_pci_iatu_write(hdev, 0x020,
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upper_32_bits(outbound_region_end_address));
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/* Increase region size */
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rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000);
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/* Enable */
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rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
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/* Return the DBI window to the default location
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* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
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* in case the firmware security is enabled
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*/
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hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
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return rc;
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}
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/**
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* hl_get_pci_memory_region() - get PCI region for given address
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* @hdev: Pointer to hl_device structure.
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* @addr: device address
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*
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* @return region index on success, otherwise PCI_REGION_NUMBER (invalid
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* region index)
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*/
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enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr)
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{
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int i;
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for (i = 0 ; i < PCI_REGION_NUMBER ; i++) {
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struct pci_mem_region *region = &hdev->pci_mem_region[i];
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if (!region->used)
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continue;
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if ((addr >= region->region_base) &&
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(addr < region->region_base + region->region_size))
|
||
|
|
return i;
|
||
|
|
}
|
||
|
|
|
||
|
|
return PCI_REGION_NUMBER;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* hl_pci_init() - PCI initialization code.
|
||
|
|
* @hdev: Pointer to hl_device structure.
|
||
|
|
*
|
||
|
|
* Set DMA masks, initialize the PCI controller and map the PCI BARs.
|
||
|
|
*
|
||
|
|
* Return: 0 on success, non-zero for failure.
|
||
|
|
*/
|
||
|
|
int hl_pci_init(struct hl_device *hdev)
|
||
|
|
{
|
||
|
|
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||
|
|
struct pci_dev *pdev = hdev->pdev;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
rc = pci_enable_device_mem(pdev);
|
||
|
|
if (rc) {
|
||
|
|
dev_err(hdev->dev, "can't enable PCI device\n");
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
pci_set_master(pdev);
|
||
|
|
|
||
|
|
rc = hdev->asic_funcs->pci_bars_map(hdev);
|
||
|
|
if (rc) {
|
||
|
|
dev_err(hdev->dev, "Failed to map PCI BAR addresses\n");
|
||
|
|
goto disable_device;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = hdev->asic_funcs->init_iatu(hdev);
|
||
|
|
if (rc) {
|
||
|
|
dev_err(hdev->dev, "PCI controller was not initialized successfully\n");
|
||
|
|
goto unmap_pci_bars;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Driver must sleep in order for FW to finish the iATU configuration */
|
||
|
|
if (hdev->asic_prop.iatu_done_by_fw)
|
||
|
|
usleep_range(2000, 3000);
|
||
|
|
|
||
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(prop->dma_mask));
|
||
|
|
if (rc) {
|
||
|
|
dev_err(hdev->dev,
|
||
|
|
"Failed to set dma mask to %d bits, error %d\n",
|
||
|
|
prop->dma_mask, rc);
|
||
|
|
goto unmap_pci_bars;
|
||
|
|
}
|
||
|
|
|
||
|
|
dma_set_max_seg_size(&pdev->dev, U32_MAX);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
unmap_pci_bars:
|
||
|
|
hl_pci_bars_unmap(hdev);
|
||
|
|
disable_device:
|
||
|
|
pci_clear_master(pdev);
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* hl_pci_fini() - PCI finalization code.
|
||
|
|
* @hdev: Pointer to hl_device structure
|
||
|
|
*
|
||
|
|
* Unmap PCI bars and disable PCI device.
|
||
|
|
*/
|
||
|
|
void hl_pci_fini(struct hl_device *hdev)
|
||
|
|
{
|
||
|
|
hl_pci_bars_unmap(hdev);
|
||
|
|
|
||
|
|
pci_clear_master(hdev->pdev);
|
||
|
|
pci_disable_device(hdev->pdev);
|
||
|
|
}
|