360 lines
8.3 KiB
C
360 lines
8.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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*
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* Authors: Younghwan Joo <yhwan.joo@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*/
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#ifndef FIMC_IS_H_
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#define FIMC_IS_H_
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#include <asm/barrier.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <media/videobuf2-v4l2.h>
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#include <media/v4l2-ctrls.h>
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#include "fimc-isp.h"
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#include "fimc-is-command.h"
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#include "fimc-is-sensor.h"
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#include "fimc-is-param.h"
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#include "fimc-is-regs.h"
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#define FIMC_IS_DRV_NAME "exynos4-fimc-is"
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#define FIMC_IS_FW_FILENAME "exynos4_fimc_is_fw.bin"
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#define FIMC_IS_SETFILE_6A3 "exynos4_s5k6a3_setfile.bin"
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#define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */
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#define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */
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#define FIMC_IS_SENSORS_NUM 2
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/* Memory definitions */
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#define FIMC_IS_CPU_MEM_SIZE (0xa00000)
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#define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1)
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#define FIMC_IS_REGION_SIZE 0x5000
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#define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
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#define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
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#define FIMC_IS_FW_INFO_LEN 31
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#define FIMC_IS_FW_VER_LEN 7
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#define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \
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FIMC_IS_FW_VER_LEN)
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#define FIMC_IS_SETFILE_INFO_LEN 39
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#define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \
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FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
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#define FIMC_IS_EXTRA_FW_SIZE 0x180000
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#define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
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/* TODO: revisit */
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#define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1)
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#define FIMC_IS_FW_SIZE_MAX (SZ_4M)
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#define FIMC_IS_FW_SIZE_MIN (SZ_32K)
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#define ATCLK_MCUISP_FREQUENCY 100000000UL
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#define ACLK_AXI_FREQUENCY 100000000UL
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enum {
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ISS_CLK_PPMUISPX,
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ISS_CLK_PPMUISPMX,
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ISS_CLK_LITE0,
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ISS_CLK_LITE1,
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ISS_CLK_MPLL,
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ISS_CLK_ISP,
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ISS_CLK_DRC,
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ISS_CLK_FD,
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ISS_CLK_MCUISP,
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ISS_CLK_GICISP,
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ISS_CLK_PWM_ISP,
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ISS_CLK_MCUCTL_ISP,
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ISS_CLK_UART,
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ISS_GATE_CLKS_MAX,
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ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
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ISS_CLK_ISP_DIV1,
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ISS_CLK_MCUISP_DIV0,
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ISS_CLK_MCUISP_DIV1,
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ISS_CLK_ACLK200,
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ISS_CLK_ACLK200_DIV,
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ISS_CLK_ACLK400MCUISP,
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ISS_CLK_ACLK400MCUISP_DIV,
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ISS_CLKS_MAX
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};
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/* The driver's internal state flags */
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enum {
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IS_ST_IDLE,
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IS_ST_PWR_ON,
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IS_ST_A5_PWR_ON,
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IS_ST_FW_LOADED,
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IS_ST_OPEN_SENSOR,
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IS_ST_SETFILE_LOADED,
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IS_ST_INIT_DONE,
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IS_ST_STREAM_ON,
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IS_ST_STREAM_OFF,
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IS_ST_CHANGE_MODE,
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IS_ST_BLOCK_CMD_CLEARED,
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IS_ST_SET_ZOOM,
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IS_ST_PWR_SUBIP_ON,
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IS_ST_END,
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};
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enum af_state {
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FIMC_IS_AF_IDLE = 0,
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FIMC_IS_AF_SETCONFIG = 1,
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FIMC_IS_AF_RUNNING = 2,
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FIMC_IS_AF_LOCK = 3,
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FIMC_IS_AF_ABORT = 4,
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FIMC_IS_AF_FAILED = 5,
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};
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enum af_lock_state {
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FIMC_IS_AF_UNLOCKED = 0,
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FIMC_IS_AF_LOCKED = 2
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};
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enum ae_lock_state {
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FIMC_IS_AE_UNLOCKED = 0,
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FIMC_IS_AE_LOCKED = 1
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};
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enum awb_lock_state {
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FIMC_IS_AWB_UNLOCKED = 0,
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FIMC_IS_AWB_LOCKED = 1
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};
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enum {
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IS_METERING_CONFIG_CMD,
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IS_METERING_CONFIG_WIN_POS_X,
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IS_METERING_CONFIG_WIN_POS_Y,
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IS_METERING_CONFIG_WIN_WIDTH,
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IS_METERING_CONFIG_WIN_HEIGHT,
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IS_METERING_CONFIG_MAX
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};
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struct is_setfile {
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const struct firmware *info;
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int state;
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u32 sub_index;
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u32 base;
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size_t size;
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};
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struct is_fd_result_header {
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u32 offset;
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u32 count;
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u32 index;
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u32 curr_index;
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u32 width;
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u32 height;
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};
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struct is_af_info {
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u16 mode;
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u32 af_state;
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u32 af_lock_state;
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u32 ae_lock_state;
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u32 awb_lock_state;
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u16 pos_x;
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u16 pos_y;
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u16 prev_pos_x;
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u16 prev_pos_y;
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u16 use_af;
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};
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struct fimc_is_firmware {
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const struct firmware *f_w;
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dma_addr_t addr;
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void *vaddr;
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unsigned int size;
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char info[FIMC_IS_FW_INFO_LEN + 1];
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char version[FIMC_IS_FW_VER_LEN + 1];
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char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
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u8 state;
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};
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struct fimc_is_memory {
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/* DMA base address */
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dma_addr_t addr;
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/* virtual base address */
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void *vaddr;
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/* total length */
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unsigned int size;
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};
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#define FIMC_IS_I2H_MAX_ARGS 12
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struct i2h_cmd {
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u32 cmd;
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u32 sensor_id;
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u16 num_args;
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u32 args[FIMC_IS_I2H_MAX_ARGS];
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};
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struct h2i_cmd {
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u16 cmd_type;
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u32 entry_id;
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};
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#define FIMC_IS_DEBUG_MSG 0x3f
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#define FIMC_IS_DEBUG_LEVEL 3
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struct fimc_is_setfile {
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const struct firmware *info;
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unsigned int state;
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unsigned int size;
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u32 sub_index;
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u32 base;
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};
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struct chain_config {
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struct global_param global;
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struct sensor_param sensor;
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struct isp_param isp;
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struct drc_param drc;
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struct fd_param fd;
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unsigned long p_region_index[2];
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};
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/**
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* struct fimc_is - fimc-is data structure
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* @pdev: pointer to FIMC-IS platform device
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* @pctrl: pointer to pinctrl structure for this device
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* @v4l2_dev: pointer to the top level v4l2_device
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* @fw: data structure describing the FIMC-IS firmware binary
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* @memory: memory region assigned for the FIMC-IS (firmware)
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* @isp: the ISP block data structure
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* @sensor: fimc-is sensor subdevice array
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* @setfile: descriptor of the imaging pipeline calibration data
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* @ctrl_handler: the v4l2 controls handler
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* @lock: mutex serializing video device and the subdev operations
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* @slock: spinlock protecting this data structure and the hw registers
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* @clocks: FIMC-LITE gate clock
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* @regs: MCUCTL mmapped registers region
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* @pmu_regs: PMU ISP mmapped registers region
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* @irq: FIMC-IS interrupt
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* @irq_queue: interrupt handling waitqueue
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* @lpm: low power mode flag
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* @state: internal driver's state flags
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* @sensor_index: image sensor index for the firmware
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* @i2h_cmd: FIMC-IS to the host (CPU) mailbox command data structure
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* @h2i_cmd: the host (CPU) to FIMC-IS mailbox command data structure
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* @fd_header: the face detection result data structure
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* @config: shared HW pipeline configuration data
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* @config_index: index to the @config entry currently in use
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* @is_p_region: pointer to the shared parameter memory region
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* @is_dma_p_region: DMA address of the shared parameter memory region
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* @is_shared_region: pointer to the IS shared region data structure
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* @af: auto focus data
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* @debugfs_entry: debugfs entry for the firmware log
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*/
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struct fimc_is {
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struct platform_device *pdev;
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struct pinctrl *pctrl;
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struct v4l2_device *v4l2_dev;
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struct fimc_is_firmware fw;
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struct fimc_is_memory memory;
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struct fimc_isp isp;
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struct fimc_is_sensor sensor[FIMC_IS_SENSORS_NUM];
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struct fimc_is_setfile setfile;
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struct v4l2_ctrl_handler ctrl_handler;
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struct mutex lock;
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spinlock_t slock;
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struct clk *clocks[ISS_CLKS_MAX];
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void __iomem *regs;
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void __iomem *pmu_regs;
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int irq;
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wait_queue_head_t irq_queue;
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u8 lpm;
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unsigned long state;
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unsigned int sensor_index;
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struct i2h_cmd i2h_cmd;
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struct h2i_cmd h2i_cmd;
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struct is_fd_result_header fd_header;
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struct chain_config config[IS_SC_MAX];
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unsigned config_index;
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struct is_region *is_p_region;
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dma_addr_t is_dma_p_region;
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struct is_share_region *is_shared_region;
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struct is_af_info af;
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struct dentry *debugfs_entry;
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};
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static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
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{
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return container_of(isp, struct fimc_is, isp);
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}
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static inline struct chain_config *__get_curr_is_config(struct fimc_is *is)
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{
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return &is->config[is->config_index];
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}
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static inline void fimc_is_mem_barrier(void)
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{
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mb();
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}
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static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
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{
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struct chain_config *cfg = &is->config[is->config_index];
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set_bit(num, &cfg->p_region_index[0]);
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}
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static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
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{
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is->is_p_region->parameter.isp.control.cmd = cmd;
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}
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static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
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{
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writel(v, is->regs + offset);
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}
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static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
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{
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return readl(is->regs + offset);
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}
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static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
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{
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writel(v, is->pmu_regs + offset);
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}
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static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
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{
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return readl(is->pmu_regs + offset);
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}
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int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
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unsigned int state, unsigned int timeout);
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int fimc_is_cpu_set_power(struct fimc_is *is, int on);
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int fimc_is_start_firmware(struct fimc_is *is);
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int fimc_is_hw_initialize(struct fimc_is *is);
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void fimc_is_log_dump(const char *level, const void *buf, size_t len);
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#endif /* FIMC_IS_H_ */
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