317 lines
8.4 KiB
C
317 lines
8.4 KiB
C
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, MIPI Alliance, Inc.
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*
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* Author: Nicolas Pitre <npitre@baylibre.com>
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*
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* I3C HCI v2.0 Command Descriptor Handling
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*
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* Note: The I3C HCI v2.0 spec is still in flux. The code here will change.
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*/
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#include <linux/bitfield.h>
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#include <linux/i3c/master.h>
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#include "hci.h"
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#include "cmd.h"
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#include "xfer_mode_rate.h"
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/*
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* Unified Data Transfer Command
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*/
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#define CMD_0_ATTR_U FIELD_PREP(CMD_0_ATTR, 0x4)
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#define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v)
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#define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v)
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#define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v)
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#define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v)
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#define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v)
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#define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v)
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#define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v)
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#define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v)
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#define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v)
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#define CMD_U2_IDB0(v) FIELD_PREP(W2_MASK( 71, 64), v)
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#define CMD_U2_BT_CMD0(v) FIELD_PREP(W2_MASK( 71, 64), v)
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#define CMD_U1_ERR_HANDLING(v) FIELD_PREP(W1_MASK( 63, 62), v)
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#define CMD_U1_ADD_FUNC(v) FIELD_PREP(W1_MASK( 61, 56), v)
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#define CMD_U1_COMBO_XFER W1_BIT_( 55)
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#define CMD_U1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v)
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#define CMD_U0_TOC W0_BIT_( 31)
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#define CMD_U0_ROC W0_BIT_( 30)
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#define CMD_U0_MAY_YIELD W0_BIT_( 29)
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#define CMD_U0_NACK_RCNT(v) FIELD_PREP(W0_MASK( 28, 27), v)
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#define CMD_U0_IDB_COUNT(v) FIELD_PREP(W0_MASK( 26, 24), v)
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#define CMD_U0_MODE_INDEX(v) FIELD_PREP(W0_MASK( 22, 18), v)
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#define CMD_U0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v)
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#define CMD_U0_DEV_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v)
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#define CMD_U0_RnW W0_BIT_( 7)
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#define CMD_U0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/*
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* Address Assignment Command
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*/
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#define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
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#define CMD_A1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v)
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#define CMD_A0_TOC W0_BIT_( 31)
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#define CMD_A0_ROC W0_BIT_( 30)
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#define CMD_A0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v)
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#define CMD_A0_ASSIGN_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v)
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#define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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static unsigned int get_i3c_rate_idx(struct i3c_hci *hci)
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{
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struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
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if (bus->scl_rate.i3c >= 12000000)
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return XFERRATE_I3C_SDR0;
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if (bus->scl_rate.i3c > 8000000)
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return XFERRATE_I3C_SDR1;
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if (bus->scl_rate.i3c > 6000000)
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return XFERRATE_I3C_SDR2;
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if (bus->scl_rate.i3c > 4000000)
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return XFERRATE_I3C_SDR3;
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if (bus->scl_rate.i3c > 2000000)
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return XFERRATE_I3C_SDR4;
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return XFERRATE_I3C_SDR_FM_FMP;
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}
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static unsigned int get_i2c_rate_idx(struct i3c_hci *hci)
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{
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struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
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if (bus->scl_rate.i2c >= 1000000)
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return XFERRATE_I2C_FMP;
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return XFERRATE_I2C_FM;
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}
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static void hci_cmd_v2_prep_private_xfer(struct i3c_hci *hci,
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struct hci_xfer *xfer,
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u8 addr, unsigned int mode,
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unsigned int rate)
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{
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u8 *data = xfer->data;
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unsigned int data_len = xfer->data_len;
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bool rnw = xfer->rnw;
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xfer->cmd_tid = hci_get_tid();
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if (!rnw && data_len <= 5) {
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xfer->cmd_desc[0] =
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CMD_0_ATTR_U |
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CMD_U0_TID(xfer->cmd_tid) |
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CMD_U0_DEV_ADDRESS(addr) |
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CMD_U0_XFER_RATE(rate) |
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CMD_U0_MODE_INDEX(mode) |
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CMD_U0_IDB_COUNT(data_len);
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xfer->cmd_desc[1] =
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CMD_U1_DATA_LENGTH(0);
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xfer->cmd_desc[2] = 0;
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xfer->cmd_desc[3] = 0;
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switch (data_len) {
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case 5:
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xfer->cmd_desc[3] |= CMD_U3_IDB4(data[4]);
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fallthrough;
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case 4:
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xfer->cmd_desc[2] |= CMD_U2_IDB3(data[3]);
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fallthrough;
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case 3:
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xfer->cmd_desc[2] |= CMD_U2_IDB2(data[2]);
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fallthrough;
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case 2:
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xfer->cmd_desc[2] |= CMD_U2_IDB1(data[1]);
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fallthrough;
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case 1:
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xfer->cmd_desc[2] |= CMD_U2_IDB0(data[0]);
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fallthrough;
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case 0:
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break;
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}
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/* we consumed all the data with the cmd descriptor */
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xfer->data = NULL;
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} else {
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xfer->cmd_desc[0] =
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CMD_0_ATTR_U |
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CMD_U0_TID(xfer->cmd_tid) |
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(rnw ? CMD_U0_RnW : 0) |
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CMD_U0_DEV_ADDRESS(addr) |
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CMD_U0_XFER_RATE(rate) |
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CMD_U0_MODE_INDEX(mode);
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xfer->cmd_desc[1] =
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CMD_U1_DATA_LENGTH(data_len);
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xfer->cmd_desc[2] = 0;
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xfer->cmd_desc[3] = 0;
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}
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}
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static int hci_cmd_v2_prep_ccc(struct i3c_hci *hci, struct hci_xfer *xfer,
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u8 ccc_addr, u8 ccc_cmd, bool raw)
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{
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unsigned int mode = XFERMODE_IDX_I3C_SDR;
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unsigned int rate = get_i3c_rate_idx(hci);
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u8 *data = xfer->data;
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unsigned int data_len = xfer->data_len;
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bool rnw = xfer->rnw;
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if (raw && ccc_addr != I3C_BROADCAST_ADDR) {
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hci_cmd_v2_prep_private_xfer(hci, xfer, ccc_addr, mode, rate);
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return 0;
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}
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xfer->cmd_tid = hci_get_tid();
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if (!rnw && data_len <= 4) {
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xfer->cmd_desc[0] =
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CMD_0_ATTR_U |
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CMD_U0_TID(xfer->cmd_tid) |
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CMD_U0_DEV_ADDRESS(ccc_addr) |
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CMD_U0_XFER_RATE(rate) |
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CMD_U0_MODE_INDEX(mode) |
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CMD_U0_IDB_COUNT(data_len + (!raw ? 0 : 1));
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xfer->cmd_desc[1] =
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CMD_U1_DATA_LENGTH(0);
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xfer->cmd_desc[2] =
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CMD_U2_IDB0(ccc_cmd);
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xfer->cmd_desc[3] = 0;
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switch (data_len) {
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case 4:
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xfer->cmd_desc[3] |= CMD_U3_IDB4(data[3]);
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fallthrough;
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case 3:
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xfer->cmd_desc[2] |= CMD_U2_IDB3(data[2]);
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fallthrough;
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case 2:
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xfer->cmd_desc[2] |= CMD_U2_IDB2(data[1]);
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fallthrough;
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case 1:
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xfer->cmd_desc[2] |= CMD_U2_IDB1(data[0]);
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fallthrough;
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case 0:
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break;
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}
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/* we consumed all the data with the cmd descriptor */
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xfer->data = NULL;
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} else {
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xfer->cmd_desc[0] =
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CMD_0_ATTR_U |
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CMD_U0_TID(xfer->cmd_tid) |
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(rnw ? CMD_U0_RnW : 0) |
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CMD_U0_DEV_ADDRESS(ccc_addr) |
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CMD_U0_XFER_RATE(rate) |
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CMD_U0_MODE_INDEX(mode) |
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CMD_U0_IDB_COUNT(!raw ? 0 : 1);
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xfer->cmd_desc[1] =
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CMD_U1_DATA_LENGTH(data_len);
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xfer->cmd_desc[2] =
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CMD_U2_IDB0(ccc_cmd);
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xfer->cmd_desc[3] = 0;
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}
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return 0;
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}
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static void hci_cmd_v2_prep_i3c_xfer(struct i3c_hci *hci,
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struct i3c_dev_desc *dev,
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struct hci_xfer *xfer)
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{
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unsigned int mode = XFERMODE_IDX_I3C_SDR;
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unsigned int rate = get_i3c_rate_idx(hci);
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u8 addr = dev->info.dyn_addr;
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hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate);
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}
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static void hci_cmd_v2_prep_i2c_xfer(struct i3c_hci *hci,
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struct i2c_dev_desc *dev,
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struct hci_xfer *xfer)
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{
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unsigned int mode = XFERMODE_IDX_I2C;
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unsigned int rate = get_i2c_rate_idx(hci);
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u8 addr = dev->addr;
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hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate);
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}
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static int hci_cmd_v2_daa(struct i3c_hci *hci)
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{
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struct hci_xfer *xfer;
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int ret;
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u8 next_addr = 0;
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u32 device_id[2];
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u64 pid;
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unsigned int dcr, bcr;
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DECLARE_COMPLETION_ONSTACK(done);
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xfer = hci_alloc_xfer(2);
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if (!xfer)
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return -ENOMEM;
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xfer[0].data = &device_id;
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xfer[0].data_len = 8;
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xfer[0].rnw = true;
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xfer[0].cmd_desc[1] = CMD_A1_DATA_LENGTH(8);
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xfer[1].completion = &done;
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for (;;) {
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ret = i3c_master_get_free_addr(&hci->master, next_addr);
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if (ret < 0)
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break;
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next_addr = ret;
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DBG("next_addr = 0x%02x", next_addr);
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xfer[0].cmd_tid = hci_get_tid();
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xfer[0].cmd_desc[0] =
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CMD_0_ATTR_A |
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CMD_A0_TID(xfer[0].cmd_tid) |
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CMD_A0_ROC;
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xfer[1].cmd_tid = hci_get_tid();
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xfer[1].cmd_desc[0] =
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CMD_0_ATTR_A |
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CMD_A0_TID(xfer[1].cmd_tid) |
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CMD_A0_ASSIGN_ADDRESS(next_addr) |
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CMD_A0_ROC |
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CMD_A0_TOC;
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hci->io->queue_xfer(hci, xfer, 2);
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, 2)) {
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ret = -ETIME;
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break;
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}
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if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) {
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ret = 0; /* no more devices to be assigned */
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break;
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}
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if (RESP_STATUS(xfer[1].response) != RESP_SUCCESS) {
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ret = -EIO;
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break;
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}
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pid = FIELD_GET(W1_MASK(47, 32), device_id[1]);
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pid = (pid << 32) | device_id[0];
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bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]);
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dcr = FIELD_GET(W1_MASK(63, 56), device_id[1]);
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DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
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next_addr, pid, dcr, bcr);
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/*
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* TODO: Extend the subsystem layer to allow for registering
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* new device and provide BCR/DCR/PID at the same time.
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*/
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ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr);
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if (ret)
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break;
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}
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hci_free_xfer(xfer, 2);
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return ret;
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}
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const struct hci_cmd_ops mipi_i3c_hci_cmd_v2 = {
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.prep_ccc = hci_cmd_v2_prep_ccc,
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.prep_i3c_xfer = hci_cmd_v2_prep_i3c_xfer,
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.prep_i2c_xfer = hci_cmd_v2_prep_i2c_xfer,
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.perform_daa = hci_cmd_v2_daa,
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};
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